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A low dielectric fluorine-doped silicon oxide (SiOF) film, which was produced by adding C2F6 to the conventional chemical vapor deposited oxide, was applied to a 0.35 µm complementary metal oxide semiconductor (CMOS) and its influence on metal oxide semiconductor field effect transistor characteristics was analyzed. A shift of the transconductance was observed when the SiOF film was used as an intermediate dielectric and the Si3N4 film as the dielectric on the metal. An improvement in speed of 13% due to the SiOF film was experimentally confirmed under the condition where the transconductance does not show a shift. Using circuit simulations, the necessity for such low dielectric films as the SiOF film, on the scaling trend in the improvement of circuit performance, was clearly shown and was also emphasized from the point of view of power reduction. It was revealed that circuit speed and power consumption of 0.35 µm CMOS were degraded if the SiOF film was not used, because the improvement of the transistor performance did not overcome the increase in interconnect capacitance due to the increase in the adjacent interconnect capacitance component.

The TiSi2 local wiring technology has been newly characterized from the viewpoints of dopant interdiffusion and power reduction. It was found that only the p+/n junction degrades when TiSi2 local wiring connects the n+ layer and p+ layer. The results of electrical measurements using a set of new test patterns suggest the reason to be that boron does not diffuse from TiSi2 to Si due to the high efficiency of TiB formation. More than a 20% reduction in power dissipation at a low-power supply voltage of 1 V was obtained, which demonstrates that the scheme is promising for low-power sub-half-micron complementary metal oxide semiconductor.

It is concluded that in a shallow junction of post-junction silicide (PJS) scheme self-aligned silicide (SALICIDE) process, the decrease of impurity concentration at the TiSi2/Si interface significantly degrades performance of metal oxide semiconductor field effect transistor (MOSFET). It is verified for the first time that this degradation is due to dopant redistribution from Si to TiSi2 during post-silicidation annealing. Dopant redistribution is strongly confirmed by evaluation of the contact resistance at the TiSi2/Si interface and analysis of impurity concentration by improved secondary ion mass spectroscopy (SIMS) technique and a two-dimensional process simulation dealing with a SALICIDE process. In order to overcome the dopant redistribution-induced degradation, a novel SALICIDE scheme, doubly source/drain-ion-implanted SALICIDE (DIS), is proposed and concluded to be an alternative to PJS scheme.