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Abstract: Typical floorplanning concerns a series of objectives, such as area, wirelength, and routability, etc., with various aspect ratios of modules in a free-outline regime. However, in a hierarchical design flow for very large ASICs and SoCs, a floorplan can be completely useless for a situation where its outline is dissatisfied. In this paper, we study the fixed-outline floorplanning problem that is more applicable to the hierarchical design style. We develop an efficient algorithm based on robust evolutionary search and achieve substantially improved success rate. We also propose a new approach to handle soft modules to further adjust the generated floorplan to fit into the prescribed chip outline. The effectiveness of our methods is demonstrated on several large cases of MCNC and GSRC benchmarks. [Copyright &y& Elsevier]

Typical floorplanning problem concerns a series of objectives, such as area, wirelength and routability, etc., without any specific constraint in a free-outline style. Entering SOC era; however, modern floorplanning takes more care of providing extra options, such as boundary constraint for I/O connections and fixed-outline constraint for hierarchical designs. It has been empirically shown that one of the modern constraints extremely restricts the solution space; that is, a large number of randomly generated floorplans might be infeasible. This paper tackles modern floorplanning with both boundary and fixed-outline constraints. A novel genetic clustering algorithm was proposed to guarantee to produce slicing floorplans with satisfying boundary constraint. By analyzing the properties of the slicing floorplan, the algorithm is effective to cluster the boundary-constrained modules into four constrained sub-floorplans. Afterward, the four sub-floorplans were combined to satisfy the boundary constraint. We then extend the algorithm with minor modification to enable the slicing floorplans with boundary constraint to be gradually fit into the desirable fixed outline. The methods were verified by using the MCNC and GSRC benchmarks, and the empirical results show that our methods can obtain promising solutions using short time. [ABSTRACT FROM AUTHOR]