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Gate diffusion input (GDI) method using a simple cell makes it possible to design low-power logic gates with reduced chip area and less complexity. In this work, a novel design of single-bit optimized reversible logic-based magnitude arithmetic unit (RMAU) circuit, using appropriate standard reversible gates with carbon nanotube (CNT) field-effect transistors (CNTFETs), based on modified-GDI (m-GDI) method for nanoscales is presented. In order to optimize the performance of the proposed circuit, and to achieve minimum power consumption and propagation delay, transistor sizes are adjusted using the non-dominated sorting genetic algorithm II (NSGA-II) in MATLAB tool. The simulation results show improvement in evaluating the figure of merits in worst-case delay and power consumption of the proposed optimized arithmetic unit, in comparison with a non-optimized RMAU circuit using a similar design method but counterpart structures. The effects of different process parameters (such as the diameter of CNTs) and voltage and temperature (PVT) variations are extensively evaluated by the Monte Carlo procedure in standard 32 nm technology utilizing the Synopsys HSPICE simulator. According to the outcomes obtained, the proposed optimized RMAU circuit is robust against PVT variations and noise-tolerable criterions, compared to those competitors with similar design in non-optimized conditions. The proposed optimized and non-optimized circuits were used in image processing as real environment assessments, and results depicted their excellent ability in being implemented in various large reversible-based applications, such as future generations of FPGA chips and CNTFET-based computers. [ABSTRACT FROM AUTHOR]

The memory includes flip flap cells which can store binary information. Therefore by designing the binary storing cell, which has the low chip area and power consumption, the high capacity memories with high performance can be presented. The gate diffusion input (GDI) method employed in designing low power logic gates can decrease the chip area and parasitic and interconnection capacitors. In this paper, the modified-GDI (m-GDI) method is used based on a basic GDI method in order to design master-slave D-Flip Flap (M/S-DFF) circuit. By employing the presented M/S-DFF circuit and the Boolean functions of m-GDI method, Random Access Memory (RAM) cell is designed. For optimizing the performance of the proposed memory cell and gaining the minimum power and propagation delay, the transistors size is adjusted with non-dominated sorting genetic algorithm-II (NSGA-II) in MATLAB software. Finally, the 4-words×4-bits RAM (4×4 RAM) cell is designed and evaluated by employing optimized RAM cell with algorithm. Due to the achieved results, the power consumption of the 4×4 RAM cell is 72.3%, while its propagation delay and Power-Delay Product (PDP) criterion are decreased 75.9% and 93%, respectively, in compare with similar cells which aren't optimized. The circuit simulation is done with Synopsys H-SPICE simulator in 32 nm CNTFET technology. For ensuring the accurate function of this algorithm, it is experimented on memory cell and decoder. By comparing NSGA-II algorithm with Multiple Objective Particle Swarm Optimization (MOPSO) algorithm, it can be observed that this method has good ability in multi-objective optimization. [ABSTRACT FROM AUTHOR]