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High Vacuum thermal evaporation was used to grow germanium islands on the silicon substrate covered by silicon oxide. The Ge nano-islands were formed by thermal annealing at different temperatures from 500 °C to 700 °C. Formation of islands was studied by various analytical techniques. The thickness of Ge layer was determined by rutherford backscattering spectroscopy (RBS). Also, combined with channeling technique, the composition and probable contaminants during synthesis processes were investigated. To explore the islands size and shape, both atomic force microscopy (AFM) and field emission scanning electron microscopy (FESEM) were used. Then the topographical images of surfaces were studied by AFM. The outcome of experimental evaluations of growth mechanism has indicated that with increasing the annealing temperature up to 700 °C, Ge islands were appeared from a uniform layer. Moreover, the statistical assessments of surfaces have shown that the nano-island's sizes can be varied from several hundred nanometers to 30 nm by growing the annealing temperature. The reduction of the size along with an increase of the number of nano-islands after each thermal treatment is a major factor to prohibit us from seeing their clear images in AFM. The possibility of running statistical estimation on islands, instead, is the powerful tool of extracting and probing the distribution and the shape of Ge island's peak in AFM images. [ABSTRACT FROM AUTHOR]

Abstract We report on formation of epi-layer of Si x Ge 1-x by taking standard procedure in CMOS technology. The competitive process of solid solubility of Ge dopant into Si and SiO 2 is the key to engineer atomically sharp, low defect very thin epitaxial layer at the interface of oxide-Si. Oxidation time process was used to control the distribution of the doped Ge ions at the interface of Si with oxide and in the oxide layer. Implanted samples (35 keV and 1 × 1016 Ge+/cm2) were oxidized at 1050 °C for 30–90 min. RBS-Channeling analysis shows two separate peaks of Ge corresponds to different depths after oxidation. Corroborate with high resolution microscopy and elemental analysis, we determined the first peak as enriched layer of Si x Ge 1-x at the interface of SiO 2 Si. Less than 10 nm epitaxially grown interfacial layer is very low in defects, and Ge ions are fully substituted into the host lattice. The second peak originated from diffusion of Ge into SiO 2 resulted in a segregated layer containing Ge in oxide film. Technological demand on forming Si x Ge 1-x layer for CMOS application through standard routes is what we address in this research. Highlights • Ge implantation and dry oxidation were used to form very thin mixed Si x Ge 1-x layer. • A rich Ge layer was formed after dry oxidation at 1050 °C. • Very thin Si x Ge 1-x layer is in epitaxial relation to the silicon substrate. • Some Ge ions are segregated in top oxide layer. [ABSTRACT FROM AUTHOR]