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The impact of electrical stress on the defect generation behaviors in thin GeO2/n-Ge gate stacks has been investigated through the measurement of the time-dependent dielectric breakdown (TDDB) and the stress-induced leakage current (SILC) characteristics. A multiple-spot breakdown (BD) event is confirmed, as well as a larger SILC generation probability compared with that in SiO2/Si structures. It is found that the slow trap generation is dominant by the amount of injected electron fluence (Qinj), and the fix charge generation is attributed to both Qinj and GeO2 thickness. [ABSTRACT FROM AUTHOR]

Abstract: The effect of constant voltage stress (CVS) on Pt/La2O3/n-Ge MOS devices biased at accumulation is investigated and reported. It is found that the stress induced leakage current (SILC) initially increases due to electron charge trapping on pre-existing bulk oxide defects. After 10s approximately, a clear decay of SILC commences which follows a t − n power law, with n lying between 0.56 and 0.75. This decay of SILC is not changed or reversed when the stressing voltage stops for short time intervals. The effect is attributed to the creation of new positively charged defects in the oxide because of the applied stressing voltage, while other mechanism such as dielectric relaxation proposed in the past is proved insufficient to explain the experimental data. Also high frequency capacitance vs. gate voltage (C–Vg ) curves measured under different CVS conditions divulge the creation of defects and charge trapping characteristics of La2O3 preciously. At low CVS exemplify the generation positively charged defects, however at higher CVS charge trapping obeys a model that was previously proposed and is a continuous distribution of traps. [Copyright &y& Elsevier]