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We developed a computer code for the thermodynamic quantum Fokker–Planck equations (T-QFPE), derived from a thermodynamic system–bath model. This model consists of an anharmonic subsystem coupled to multiple Ohmic baths at different temperatures, which are connected to or disconnected from the subsystem as a function of time. The code numerically integrates the T-QFPE and their classical expression to simulate isothermal, isentropic, thermostatic, and entropic processes in both quantum and classical cases. The accuracy of the results was verified by comparing the analytical solutions of the Brownian oscillator. In addition, we illustrated a breakdown of the Markovian Lindblad-master equation in the pure quantum regime. As a demonstration, we simulated a thermostatic Stirling engine employed to develop non-equilibrium thermodynamics [S. Koyanagi and Y. Tanimura, J. Chem. Phys. 161, 114113 (2024)] under quasi-static conditions. The quasi-static thermodynamic potentials, described as intensive and extensive variables, were depicted as work diagrams. In the classical case, the work done by the external field is independent of the system–bath coupling strength. In contrast, in the quantum case, the work decreases as the coupling strength increases due to quantum entanglement between the subsystem and bath. The codes were developed for multicore processors using Open Multi-Processing (OpenMP) and for graphics processing units using the Compute Unified Device Architecture. These codes are provided in the supplementary material. [ABSTRACT FROM AUTHOR]

Electric vehicles (EVs) are becoming more and more popular as they provide significant environmental benefits compared to fossil-fuel vehicles. However, they represent substantial loads on the power grid, and the scheduling of EV charging can be a challenge, especially in large parking lots. This paper presents a metaheuristic-based approach parallelized on multicore processors (CPU) and graphics processing units (GPU) to optimize the scheduling of EV charging in a single smart parking lot. The proposed method uses a particle swarm optimization algorithm that takes as input the arrival time, the departure time, and the power demand of the vehicles and produces an optimized charging schedule for all vehicles in the parking lot, which minimizes the overall charging cost while respecting the chargers' capacity and the parking lot feeder capacity. The algorithm exploits task-level parallelism for the multicore CPU implementation and data-level parallelism for the GPU implementation. The proposed algorithm is tested in simulation on parking lots containing 20 to 500 EVs. The parallel implementation on CPUs provides a speedup of 7.1x, while the implementation on a GPU provides a speedup of up to 247.6x. The parallel implementation on a GPU is able to optimize the charging schedule for a 20-EV parking lot in 0.87 s and a 500-EV lot in just under 30 s. These runtimes allow for real-time computation when a vehicle arrives at the parking lot or when the electricity cost profile changes. [ABSTRACT FROM AUTHOR]

Four‐Wave Mixing (FWM) is one of the non‐linear phenomena affecting long‐reach communication systems and high bandwidth. Research communities use simulation tools for parameter optimization. Unfortunately, such a simulation is time‐consuming and requires more time as the number of channels increases. This paper proposes two fast implementations of Dense Wavelength Division Multiplexing (DWDM) system, limited by FWM and the intrinsic Amplified Spontaneous Emission (ASE) noise of optical amplifiers employed in each segment. Additionally, this work compares the efficiency and speed improvement of the proposed parallelization model versus an earlier sequential model. We present the computational complexity analysis of sequential and parallel models. The paper considers two different parallel implementations: a multicore processor using Open MultiProcessing (OpenMP) and Compute Unified Device Architecture (CUDA), which is based on the use of a Graphics Processing Unit (GPU). Results show that parallelism using CUDA improves by up to 70 times the simulation performance compared to the sequential model. Parallelism with CUDA is up to 15 times compared to OpenMP using 12 logical processors. It is possible to simulate an increased number of channels within our parallel execution, which was impractical in the sequential simulation. [ABSTRACT FROM AUTHOR]

Phylogenies are central to many research areas in biology and commonly estimated using likelihood-based methods. Unfortunately, any likelihood-based method, including Bayesian inference, can be restrictively slow for large datasets—with many taxa and/or many sites in the sequence alignment—or complex substitutions models. The primary limiting factor when using large datasets and/or complex models in probabilistic phylogenetic analyses is the likelihood calculation, which dominates the total computation time. To address this bottleneck, we incorporated the high-performance phylogenetic library BEAGLE into RevBayes , which enables multi-threading on multi-core CPUs and GPUs, as well as hardware specific vectorized instructions for faster likelihood calculations. Our new implementation of RevBayes+BEAGLE retains the flexibility and dynamic nature that users expect from vanilla RevBayes. In addition, we implemented native parallelization within RevBayes without an external library using the message passing interface (MPI); RevBayes+MPI. We evaluated our new implementation of RevBayes+BEAGLE using multi-threading on CPUs and 2 different powerful GPUs (NVidia Titan V and NVIDIA A100) against our native implementation of RevBayes+MPI. We found good improvements in speedup when multiple cores were used, with up to 20-fold speedup when using multiple CPU cores and over 90-fold speedup when using multiple GPU cores. The improvement depended on the data type used, DNA or amino acids, and the size of the alignment, but less on the size of the tree. We additionally investigated the cost of rescaling partial likelihoods to avoid numerical underflow and showed that unnecessarily frequent and inefficient rescaling can increase runtimes up to 4-fold. Finally, we presented and compared a new approach to store partial likelihoods on branches instead of nodes that can speed up computations up to 1.7 times but comes at twice the memory requirements. [ABSTRACT FROM AUTHOR]

Summary: Deflate coding is a very popular lossless data compression method used in zlib, gzip (GNU zip), and zip, which performs the LZSS compression algorithm with Huffman coding. Deflate encoding and decoding involve sequential operations and their parallel acceleration using a GPU is quite hard. The main purpose of this paper is to present GPU implementations for encoding and decoding of Deflate coding. For efficient GPU implementations of Deflate coding, we have used multiple small hash tables for finding matching subsequences in the dictionary by multiple threads in parallel and applied the Single Kernel Soft Synchronization (SKSS) technique to fully utilize GPU computing resources. We have also adopted Huffman coding with gap arrays to accelerate parallel Huffman decoding. We have evaluated the performance of our GPU implementations using an NVIDIA A100 GPU and compared them with parallel/sequential Deflate encoding and decoding on the Intel X86 multicore CPUs using multiple threads/a single thread. Our GPU implementation of Deflate decoding is 1.66x–8.33x faster than the multiple thread implementation and 4.13x–36.56x faster than the single thread implementation. [ABSTRACT FROM AUTHOR]

Summary: The Floyd‐Warshall algorithm is a well‐known algorithm to compute the distance of all pairs of nodes of a graph. The Blocked Floyd‐Warshall algorithm, a variant of the Floyd‐Warshall has been proposed to accelerate the Floyd‐Warshall algorithm by means of a graphics processing unit (GPU) architecture. The previously published GPU implementations for the Blocked Floyd‐Warshall algorithm perform many separated kernel calls for costly barrier synchronization. The main contribution of this article is to present efficient implementations of the Blocked Floyd‐Warshall algorithm, which performs no barrier synchronization and invokes only one kernel call. Experimental results using NVIDIA Tesla V100 show that our implementation runs 1.05‐1.31 times faster than the previously published one. Our implementation with SIMD functions also runs 1.00‐1.28 times faster than it. Second, we propose efficient GPU implementations to execute the Blocked Floyd‐Warshall algorithm for many graphs at the same time. From the experimental results, our single kernel implementation runs 1.03‐1.60 times faster than multiple kernel one. In terms of implementations with SIMD functions, our single kernel implementation runs 1.01‐1.89 times faster than it. We also propose the low‐latency implementations for many graphs. Finally, we implemented the parallel Floyd‐Warshall algorithm on the multicore processors. [ABSTRACT FROM AUTHOR]

The energy consumption of Information and Communications Technology (ICT) presents a new grand technological challenge. The two main approaches to tackle the challenge include the development of energy-efficient hardware and software. The development of energy-efficient software employing application-level energy optimization techniques has become an important category owing to the paradigm shift in the composition of digital platforms from single-core processors to heterogeneous platforms integrating multicore CPUs and graphics processing units (GPUs). In this work, we present an overview of application-level bi-objective optimization methods for energy and performance that address two fundamental challenges, non-linearity and heterogeneity, inherent in modern high-performance computing (HPC) platforms. Applying the methods requires energy profiles of the application's computational kernels executing on the different compute devices of the HPC platform. Therefore, we summarize the research innovations in the three mainstream component-level energy measurement methods and present their accuracy and performance tradeoffs. Finally, scaling the optimization methods for energy and performance is crucial to achieving energy efficiency objectives and meeting quality-of-service requirements in modern HPC platforms and cloud computing infrastructures. We introduce the building blocks needed to achieve this scaling and conclude with the challenges to scaling. Briefly, two significant challenges are described, namely fast optimization methods and accurate component-level energy runtime measurements, especially for components running on accelerators. [ABSTRACT FROM AUTHOR]

Graphics Processing Units (GPUs) are designed to process numerically intensive applications and specially customized with additional computational power to achieve efficient rendering of 3D applications. Shaders are basically the computer programs that run on graphics rendering pipeline and inform about how to process and render each pixel, to perform efficient rendering of 3D applications. Shaders included in our Geometric complexity, texture resolution, per-pixel lighting. These shaders expose GPUs to suffer more power utilization during rendering process. In this paper, initially GPU power usage is investigated at run-time for rendering configuration to define shader parameters on a 3D scene and then power prediction model is proposed at different shader calls on GPU to generate power-aware dynamically reconfigurable rendering model. In the implementation process we integrate the TensorFlow management library routines and dynamic voltage and frequency scheduling (DVFS) mechanism to improve efficiency in rendering process and reach optimal power savings. To analyze the power efficiency of GPUs, shader parameters such as geometric complexity, texture resolution, per-pixel lighting, filtering that expose more towards power consumption are experimented with common GPU workloads during rendering process, then frequency and voltage is altered based on the framerate monitoring. Also in addition to this the frame rate is monitored and maintained in such a way that GPU frequency is adjusted in parallel if the framerate is within the acceptable range so that unnecessary power usage is reduced. During the experimental tests a lower limit of 30 frames per second and upper limit of 60 frames per second is configured. The GPU frequency is reduced if the existing framerate is greater than upper configured limit and frequency range is increased if framerate is below the configured lower limit. Compared with the previous state of art, results show power savings around 40% and improved speedup in computation time with maximum quality of a 3D scene. [ABSTRACT FROM AUTHOR]

The increasing complexity of modern AC/DC power systems poses a significant challenge to a fast solution of large-scale transient stability simulation problems. This paper proposes the hybrid parallel-in-time-and-space (PiT+PiS) transient simulation on the CPU-GPU platform to thoroughly exploit the parallelism from time and spatial perspectives, thereby fully utilizing parallel processing hardware. The respective electromechanical and electromagnetic aspects of the AC and DC grids demand a combination of transient stability (TS) simulation and electromagnetic transient (EMT) simulation to reflect both system-level and equipment-level transients. The TS simulation is performed on GPUs in the co-simulation, while the Parareal parallel-in-time (PiT) scheduling and EMT simulation are conducted on CPUs. Therefore, the heterogeneous CPU-GPU scheme can utilize asynchronous computing features to offset the data transfer latency between different processors. Higher scalability and extensibility than GPU-only dynamic parallelism design is achieved by utilizing concurrent GPU streams for coarse-grid and fine-grid computation. A synthetic AC/DC grid based on IEEE-118 Bus and CIGRÉ DCS2 systems showed a good accuracy compared to commercial TSAT software, and a speedup of 165 is achieved with 48 IEEE-118 Bus systems and 192 201-Level detail-modeled MMCs. Furthermore, the proposed method is also applicable to multi-GPU implementation where it demonstrates decent efficacy. [ABSTRACT FROM AUTHOR]

Summary: We contribute to the optimization of the sparse matrix‐vector product by introducing a variant of the coordinate sparse matrix format that balances the workload distribution and compresses both the indexing arrays and the numerical information. Our approach is multi‐platform, in the sense that the realizations for (general‐purpose) multicore processors as well as graphics accelerators (GPUs) are built upon common principles, but differ in the implementation details, which are adapted to avoid thread divergence in the GPU case or maximize compression element‐wise (i.e., for each matrix entry) for multicore architectures. Our evaluation on the two last generations of NVIDIA GPUs as well as Intel and AMD processors demonstrate the benefits of the new kernels when compared with the optimized implementations of the sparse matrix‐vector product in NVIDIA's cuSPARSE and Intel's MKL, respectively. [ABSTRACT FROM AUTHOR]

Power flow (PF) calculation provides the basis for the steady-state power system analysis and is the backbone of many power system applications ranging from operations to planning. The calculated voltage and power values by PF are essential to determining the system condition and ensuring the security and stability of the grid. The emergence of multicore processors provides an opportunity to accelerate the speed of PF computation and, consequently, improve the performance of applications that run PF within their processes. This paper introduces a fast Newton-Raphson power flow implementation on multicore CPUs by combining sparse matrix techniques, mathematical methods, and parallel processing. Experimental results validate the effectiveness of our approach by finding the power flow solution of a synthetic U.S. grid test case with 82,000 buses in just 1.8 seconds. [ABSTRACT FROM AUTHOR]

Datacenters use GPUs to provide the significant computing throughput required by emerging user-facing services. The diurnal user access pattern of user-facing services provides a strong incentive to co-located applications for better GPU utilization, and prior work has focused on enabling co-location on multicore processors and traditional non-preemptive GPUs. However, current GPUs are evolving towards spatial multitasking and introduce a new set of challenges to eliminate QoS violations. To address this open problem, we explore the underlying causes of QoS violation on spatial multitasking GPUs. In response to these causes, we propose C-Laius, a runtime system that carefully allocates the computation resource to co-located applications for maximizing the throughput of batch applications while guaranteeing the required QoS of user-facing services. C-Laius not only allows co-locating one user-facing application with multiple batch applications, but also supports the co-location of multiple user-facing applications with batch applications. In the case of a single co-located user-facing application, our evaluation on an Nvidia RTX 2080Ti GPU shows that C-Laius improves the utilization of spatial multitasking GPUs by 20.8 percent, while achieving the 99%-ile latency target for user-facing services. As to the case of multiple co-located user-facing applications, C-Laius ensures no violation of QoS while improving the accelerator utilization by 35.9 percent on average. [ABSTRACT FROM AUTHOR]

Increasing attention has been attracted to the research of ultrasound computed tomography (USCT). This article reports the design considerations and implementation details of a novel USCT research system named UltraLucid, which aims to provide a user-friendly platform for researchers to develop new algorithms and conduct clinical trials. The modular design strategy is adopted to make the system highly scalable. A prototype has been assembled in our laboratory, which is equipped with a 2048-element ring transducer, 1024 transmit (TX) channels, 1024 receive (RX) channels, two servers, and a control unit. The prototype can acquire raw data from 1024 channels simultaneously using a modular data acquisition and a transfer system, consisting of 16 excitation and data acquisition (EDAQ) boards. Each EDAQ board has 64 independent TX and RX channels and 4-Gb Ethernet interfaces for raw data transmission. The raw data can be transferred to two servers at a theoretical rate of 64 Gb/s. Both servers are equipped with a 10.9-TB solid-state drive (SSD) array that can store raw data for offline processing. Alternatively, after processing by onboard field-programmable gate arrays (FPGAs), the raw data can be processed online using multicore central processing units (CPUs) and graphics processing units (GPUs) in each server. Through control software running on the host computer, the researchers can configure parameters for transmission, reception, and data acquisition. Novel TX–RX scheme and coded imaging can be implemented. The modular hardware structure and the software-based processing strategy make the system highly scalable and flexible. The system performance is evaluated with phantoms and in vivo experiments. [ABSTRACT FROM AUTHOR]

In this article, we present a novel distributed memory tridiagonal solver library, targeting large-scale systems based on modern multicore and many-core processor architectures. The library uses methods based on both approximate and exact algorithms. Performance comparisons with the state of the art, using both a large Cray EX system and a GPU cluster show the algorithmic tradeoffs required at increasing machine scale to achieve good performance, particularly considering the advent of exascale systems. [ABSTRACT FROM AUTHOR]

Extracting association rules from huge amounts of data is an essential method in data mining that can provide valuable knowledge from datasets for various applications. In addition to a variety of traditional and parallel association rule mining (ARM) methods, some studies have also been represented in the literature to extract association rules from datasets using multi-core processors combining GPU-CPU (graphics processing unit-central processing unit) and FPGA-CPU (field programmable gate array-central processing unit). These parallel methods have been utilized to speed up the process of ARM, including its major phase, frequent itemset mining (FIM). The use of multiple GPUs for ARM and FIM has been usually in the cluster form, and the simultaneous use of multiple GPUs on a single system has not been extensively used to extract the set of association rules. Due to the huge volume of big data, finding more efficient and faster ARM and FIM methods is still of interest to researchers. In this paper, the butterfly optimization algorithm (BOA), which has an acceptable accuracy and speed in solving optimization problems, is used for ARM. In this study, an efficient platform including a single CPU and three parallel GPUs are employed to parallelize ARM using BOA. The main feature of the proposed method is the use of parallel GPUs on a single computer, to speed up the process, and the use of the CPU as a synchronizer. Since the GPUs reduce the runtime by executing similar duplicate structures, the proposed model speeds up the mining process and prevents computing overload on the CPU. All three phases of the algorithm are implemented on the parallel graphics cards to increase the performance. The evaluation of the proposed method and its comparison with the BSO- and GBSO-Miner methods show its better performance in terms of accuracy and execution time. [ABSTRACT FROM AUTHOR]

Summary: Reverse time migration (RTM) simulation is the basis of the seismic imaging tools used by the oil and gas industry. Developers have been porting their simulations to the new high‐performance computing architectures, providing faster and more accurate results at each new generation. However, several challenges arrive when trying to achieve high performance on these new architectures. The first one is to choose the architecture that best fits the kind of simulation. After that, researchers should choose the API used to implement the simulation code. These two decisions are strongly related to the effort, performance, and energy efficiency of the simulations. In this article, we propose three optimizations for an oil and gas application, which reduce the floating‐point operations by changing the equation derivatives. We evaluate these optimizations in different multicore and GPU architectures, investigating the impact of different APIs on the performance, energy efficiency, and portability of the code. Our experimental results show that the dedicated CUDA implementation running on the NVIDIA Volta architecture has the best performance and energy efficiency for RTM on GPUs, while the OpenMP version is the best for Intel Broadwell in the multicore. Also, the OpenACC version, which has a lower programming effort and executes on both architectures, has an up to 20% better performance and energy efficiency than the nonportable ones. [ABSTRACT FROM AUTHOR]

Games have been one of the most popular applications on smartphones. In order to meet the increasing computational complexity of mobile games, smartphones are now equipped with heterogeneous CPU multi-core architectures like big.LITTLE as well as high-performance GPUs. However, the integrated CPUs and GPUs drain the battery quickly, which has become a bottleneck for improving user experience. In addition to traditional Dynamic Voltage and Frequency Scaling (DVFS) technique for CPUs and GPUs power reduction, heterogeneous multi-core processors, such as the big.LITTLE architecture, have been designed to offer more opportunity for performance-energy tradeoffs. But current processor governors in smartphones can not exploit these power-saving mechanisms wisely, causing considerable energy waste. In this article, we propose a CPU-GPU governing framework that recognizes the performance demand for different game scenes, and select the most energy-efficient hardware configuration for the corresponding scenes. We implement our framework on an ODROID-XU4 mobile platform, and the experiments show that our framework can achieve 26.7, 16.6, and 10.5 percent power saving on average without compromising user experience when compared to the default governor used in our platform and two governors proposed by other researchers, respectively. [ABSTRACT FROM AUTHOR]

Many current system-on-chip (SoC) devices are composed of low-power multicore processors combined with a small graphics accelerator (or GPU) offering a trade-off between computational capacity and low-power consumption. In this context, spatial audio methods such as wave field synthesis (WFS) can benefit from a distributed system composed of several SoCs that collaborate to tackle the high computational cost of rendering virtual sound sources. This paper aims at evaluating important aspects dealing with a distributed WFS implementation that runs over a network of Jetson Nano boards composed of embedded GPU-based SoCs: computational performance, energy efficiency, and synchronization issues. Our results show that the maximum efficiency is obtained when the WFS system operates the GPU frequency at 691.2 MHz, achieving 11 sources-per-Watt. Synchronization experiments using the NTP protocol show that the maximum initial delay of 10 ms between nodes does not prevent us from achieving high spatial sound quality. [ABSTRACT FROM AUTHOR]

Both features allow the distribution of GPU tasks dynamically and flexibly across computing nodes and the multitenant usage of GPU resources, improving their flexibility and utilization in high-performance and cloud computing. Heterogeneity is emerging as one of the most profound and challenging characteristics of today's and tomorrow's parallel and distributed computing environments, presenting new and exciting opportunities for their development. Performance improves by more than 50 times on a high-end GPU and more than four times with a GPU platform that consumes almost five times I less i power than the CPU one. [Extracted from the article]

With the commencement of the exascale computing era, we realize that the majority of the leadership supercomputers are heterogeneous and massively parallel. Even a single node can contain multiple co-processors such as GPUs and multiple CPU cores. For example, ORNL's Summit accumulates six NVIDIA Tesla V100 GPUs and 42 IBM Power9 cores on each node. Synchronizing across compute resources of multiple nodes can be prohibitively expensive. Hence, it is necessary to develop and study asynchronous algorithms that circumvent this issue of bulk-synchronous computing. In this study, we examine the asynchronous version of the abstract Restricted Additive Schwarz method as a solver. We do not explicitly synchronize, but allow the communication between the sub-domains to be completely asynchronous, thereby removing the bulk synchronous nature of the algorithm. We accomplish this by using the one-sided Remote Memory Access (RMA) functions of the MPI standard. We study the benefits of using such an asynchronous solver over its synchronous counterpart. We also study the communication patterns governed by the partitioning and the overlap between the sub-domains on the global solver. Finally, we show that this concept can render attractive performance benefits over the synchronous counterparts even for a well-balanced problem. [ABSTRACT FROM AUTHOR]

Gridding operation, which is to map non-uniform data samples on to a uniformly distributed grid, is one of the key steps in radio astronomical data reduction process. One of the main bottlenecks of gridding is the poor computing performance, and a typical solution for such performance issue is the implementation of multicore CPU platforms. Although such a method could usually achieve good results, in many cases, the performance of gridding is still restricted to an extent due to the limitations of CPU, since the main workload of gridding is a combination of a large number of single instruction, multidata stream operations, which is more suitable for GPU, rather than CPU implementations. To meet the challenge of massive data gridding for the modern large single-dish radio telescopes, e.g. the Five-hundred-meter Aperture Spherical radio Telescope, inspired by existing multicore CPU gridding algorithms such as Cygrid, here we present an easy-to-install, high-performance, and open-source convolutional gridding framework , HCGrid , in CPU-GPU heterogeneous platforms. It optimizes data search by employing multithreading on CPU, and accelerates the convolution process by utilizing massive parallelization of GPU. In order to make HCGrid a more adaptive solution, we also propose the strategies of thread organization and coarsening, as well as optimal parameter settings under various GPU architectures. A thorough analysis of computing time and performance gain with several GPU parallel optimization strategies show that it can lead to excellent performance in hybrid computing environments. [ABSTRACT FROM AUTHOR]

The energy efficiency of GPU architectures has emerged as an essential aspect of computer system design. In this article, we explore the energy benefits of reducing the GPU chip’s voltage to the safe limit, i.e., $V_{\min }$ point, using predictive software techniques. We perform such a study on several commercial off-the-shelf GPU cards. We find that there exists about 20% voltage guardband on those GPUs spanning two architectural generations, which, if “eliminated” entirely, can result in up to 25% energy savings on one of the studied GPU cards. Our measurement results unveil a program dependent $V_{\min }$ behavior across the studied applications, and the exact improvement magnitude depends on the program’s available guardband. We make fundamental observations about the program-dependent $V_{\min }$ behavior. We experimentally determine that the voltage noise has a more substantial impact on $V_{\min }$ compared to the process and temperature variation, and the activities during the kernel execution cause large voltage droops. From these findings, we show how to use kernels’ microarchitectural performance counters to predict its $V_{\min }$ value accurately. The average and maximum prediction errors are 0.5% and 3%, respectively. The accurate $V_{\min }$ prediction opens up new possibilities of a cross-layer dynamic guardbanding scheme for GPUs, in which software predicts and manages the voltage guardband, while the functional correctness is ensured by a hardware safety net mechanism. [ABSTRACT FROM AUTHOR]

In this paper, we describe high-performance methods for recording sea-surface spectra from space images for solving problems of operational oceanography. Algorithms and research software that implement methods for the operational recovery of the characteristics of the sea surface from space images are developed. These algorithms are tested and their performance are estimated using experimental data. The research software is designed to operate with multicore processors. Based on numerical experiments, the software was found to perform within a 1% error spectra reconstruction of slopes and elevations of the sea surface using the high-performance methods that are developed. Computational experiments demonstrated a significant increase in the performance of registering the spectra of slopes and elevations of the sea surface from the spectra of space images due to the parallelization of computations: by 5 times using only the central processor of a standard desktop computer and by more than 12 times using a graphics processor with CUDA technology. Examples of the application of the developed algorithms for monitoring the vast waters of the Black Sea and the Pacific Ocean are given. [ABSTRACT FROM AUTHOR]

Magnetic resonance imaging (MRI) of the brain is a safe and painless test that uses a magnetic field and radio waves to produce detailed images of the brain. FreeSurfer is a tool neuroscientists use to create models of structures in the brain. An average MRI analysis using FreeSurfer takes around 7 h on a central processing unit with 4 cores. Since execution time is so high, researchers are working on different ways to parallelize the software. Most efforts are concentrated on parallelization using multicore, specifically with OpenMP (an implementation of multithreading) reducing execution time around 20%. In this paper, we further accelerate the analysis time for FreeSurfer using the manycore processors, special multicore processors containing from dozens to thousands simpler independent cores. Specifically, we will use graphics processing unit (GPU) a manycore with thousands of simpler cores. Multicore and manycore using GPU acceleration are not mutually exclusive (we will call it GPU acceleration from now on), and we present an implementation that uses both types of accelerations (multicore and GPU). Results show that execution times using both accelerations reduce the analysis time by 70%. Manycore processors are specialist multicore processors designed for a high degree of parallel processing, containing numerous simpler, independent processor cores (from a few tens of cores to thousands or more). Manycore processors are used extensively in embedded computers and high-performance computing. [ABSTRACT FROM AUTHOR]

With semiconductor technology gradually approaching its physical and thermal limits, recent supercomputers have adopted major architectural changes to continue increasing the performance through more power-efficient heterogeneous many-core systems. Examples include Sunway TaihuLight that has four management processing elements (MPEs) and 256 computing processing elements (CPEs) inside one processor and Summit that has two central processing units (CPUs) and six graphics processing units (GPUs) inside one node. Meanwhile, current high-resolution Earth system models that desperately require more computing power generally consist of millions of lines of legacy code developed for traditional homogeneous multicore processors and cannot automatically benefit from the advancement of supercomputer hardware. As a result, refactoring and optimizing the legacy models for new architectures become key challenges along the road of taking advantage of greener and faster supercomputers, providing better support for the global climate research community and contributing to the long-lasting societal task of addressing long-term climate change. This article reports the efforts of a large group in the International Laboratory for High-Resolution Earth System Prediction (iHESP) that was established by the cooperation of Qingdao Pilot National Laboratory for Marine Science and Technology (QNLM), Texas A&M University (TAMU), and the National Center for Atmospheric Research (NCAR), with the goal of enabling highly efficient simulations of the high-resolution (25 km atmosphere and 10 km ocean) Community Earth System Model (CESM-HR) on Sunway TaihuLight. The refactoring and optimizing efforts have improved the simulation speed of CESM-HR from 1 SYPD (simulation years per day) to 3.4 SYPD (with output disabled) and supported several hundred years of pre-industrial control simulations. With further strategies on deeper refactoring and optimizing for remaining computing hotspots, as well as redesigning architecture-oriented algorithms, we expect an equivalent or even better efficiency to be gained on the new platform than traditional homogeneous CPU platforms. The refactoring and optimizing processes detailed in this paper on the Sunway system should have implications for similar efforts on other heterogeneous many-core systems such as GPU-based high-performance computing (HPC) systems. [ABSTRACT FROM AUTHOR]

On-chip photonics is a disruptive technology, and such NoCs are superior to traditional electrical NoCs in terms of latency, power, and bandwidth. Hence, researchers have proposed a wide variety of optical networks for multicore processors. The high bandwidth and low latency features of photonic NoCs have led to the overall improvement in the system performance. However, there are very few proposals that discuss the usage of optical interconnects in Graphics Processor Units (GPUs). GPUs can also substantially gain from such novel technologies, because they need to provide significant computational throughput without further stressing their power budgets. The main shortcoming of optical networks is their high static power usage, because the lasers are turned on all the time by default, even when there is no traffic inside the chip, and thus sophisticated laser modulation schemes are required. Such modulation schemes base their decisions on an accurate prediction of network traffic in the future. In this article, we propose an energy-efficient and scalable optical interconnect formodern GPUs called GPUOPT that smartly creates an overlay network by dividing the symmetric multiprocessors (SMs) into clusters. It furthermore has separate sub-networks for coherence and non-coherence traffic. To further increase the throughput, we connect the of-chip memory with optical links as well. Subsequently, we show that traditional laser modulation schemes (for reducing static power consumption) that were designed for multicore processors are not that effective for GPUs. Hence, there was a need to create a bespoke scheme for predicting the laser power usage in GPUs. Using this set of techniques, we were able to improve the performance of a modern GPU by 45% as compared to a state-of-the-art electrical NoC. Moreover, as compared to competing optical NoCs for GPUs, our scheme reduces the laser power consumption by 67%, resulting in a net 65% reduction in ED2 for a suite of Rodinia benchmarks. [ABSTRACT FROM AUTHOR]

Immersed boundary-lattice Boltzmann method (IB-LBM) has become a popular method for studying fluid-structure interaction (FSI) problems. However, the performance issues of the IB-LBM have to be considered when simulating the practical problems. The Graphics Processing Units (GPUs) from NVIDIA offer a possible solution for the parallel computing, while the CPU is a multicore processor that can also improve the parallel performance. This paper proposes a parallel algorithm for IB-LBM on a CPU-GPU heterogeneous platform, in which the CPU not only controls the launch of the kernel function but also performs calculations. According to the relatively local calculation characteristics of IB-LBM and the features of the heterogeneous platform, the flow field is divided into two parts: GPU computing domain and CPU computing domain. CUDA and OpenMP are used for parallel computing on the two computing domains, respectively. Since the calculation time is less than the data transmission time, a buffer is set at the junction of two computational domains. The size of the buffer determines the number of the evolution of the flow field before the data exchange. Therefore, the number of communications can be reduced by increasing buffer size. The performance of the method was investigated and analyzed using the traditional metric MFLUPS. The new algorithm is applied to the computational simulation of red blood cells (RBCs) in Poiseuille flow and through a microchannel. [ABSTRACT FROM AUTHOR]

Stochastic differential equations (SDEs) are widely used to model systems affected by random processes. In general, the analysis of an SDE model requires numerical solutions to be generated many times over multiple parameter combinations. However, this process often requires considerable computational resources to be practicable. Due to the embarrassingly parallel nature of the task, devices such as multi-core processors and graphics processing units (GPUs) can be employed for acceleration. Here, we present SODECL (https://github.com/avramidis/sodecl), a software library that utilizes such devices to calculate multiple orbits of an SDE model. To evaluate the acceleration provided by SODECL, we compared the time required to calculate multiple orbits of an exemplar stochastic model when one CPU core is used, to the time required when using all CPU cores or a GPU. In addition, to assess scalability, we investigated how model size affected execution time on different parallel compute devices. Our results show that when using all 32 CPU cores of a high-end high-performance computing node, the task is accelerated by a factor of up to ≈6.7, compared to when using a single CPU core. Executing the task on a high-end GPU yielded accelerations of up to ≈4.5, compared to a single CPU core. [ABSTRACT FROM AUTHOR]

An important concept in finite state machine based testing is synchronization which is used to initialize an implementation to a particular state. Usually, synchronizing sequences are used for this purpose and the length of the sequence used is important since it determines the cost of the initialization process. Unfortunately, the shortest synchronization sequence problem is NP-Hard. Instead, heuristics are used to generate short sequences. However, the cubic complexity of even the fastest heuristic algorithms can be a problem in practice. In order to scale the performance of the heuristics for generating short synchronizing sequences, we propose algorithmic improvements together with a parallel implementation of the cheapest heuristics existing in the literature. To identify the bottlenecks of these heuristics, we experimented on random and slowly synchronizing automata. The identified bottlenecks in the algorithms are improved by using algorithmic modifications. We also implement the techniques on multicore CPUs and Graphics Processing Units (GPUs) to take benefit of the modern parallel computation architectures. The sequential implementation of the heuristic algorithms are compared to our parallel implementations by using a test suite consisting of 1200 automata. The speedup values obtained depend on the size and the nature of the automaton. In our experiments, we observe speedup values as high as 340x by using a 16-core CPU parallelization, and 496x by using a GPU. Furthermore, the proposed methods scale well and the speedup values increase as the size of the automata increases. • We propose algorithmic improvements together with an efficient parallelization approach for synchronizing sequence heuristics. • We experimented on random and slowly synchronizing automata. • We implement the proposed techniques on multicore CPUs and Graphics Processing Units (GPUs) to take benefit of the modern parallel architectures. • With the proposed techniques, we observe speedup values as high as 340x by using a 16-core CPU parallelization, and 496x by using a GPU. • The proposed methods scale well and the speedup values increase as the size of the automata increases. [ABSTRACT FROM AUTHOR]

The state-of-the-art supercomputing infrastructures are equipped with accelerators, such as graphics processing units (GPUs), that operate as coprocessors for each workstation of the distributed memory system. The multi-projection type methods are a class of algebraic domain decomposition methods based on semi-aggregation techniques. The multi-projection type methods have improved convergence behavior, as the number of subdomains increases, due to the corresponding augmentation of the semi-aggregated local linear systems with more coarse components, while the number of fine components is reduced. Moreover, limited amount of communications among the workstations is required by the proposed method. The utilization of the available GPUs allows an increase in the number of subdomains along with finer-grained parallelism, leading to improved performance. A load-balancing algorithm that ensures the concurrency of the computations on multicore processors and GPUs is proposed. Flexible parallel preconditioned Krylov subspace iterative methods enhanced with multi-projection type methods have been designed appropriately in order to have improved performance, compared to CPU-only or GPU-only executions, by exploiting the available CPUs and GPUs of the distributed memory system concurrently. The unsymmetric local linear systems are solved by the preconditioned Bi-Conjugate Gradient STABilized (BiCGSTAB) method enhanced with the modified generic factored approximate sparse inverse preconditioner, whereas the preconditioned conjugate gradient (CG) method along with the symmetric factored approximate sparse inverse preconditioner is used for the symmetric positive definite local coefficient matrices. Numerical results regarding the convergence behavior, the performance, and the scalability of the proposed method for several problems are given. [ABSTRACT FROM AUTHOR]

The factorization of sparse symmetric indefinite systems is particularly challenging since pivoting is required to maintain stability of the factorization. Pivoting techniques generally offer limited parallelism and are associated with significant data movement hindering the scalability of these methods. Variants of the threshold partial pivoting (TPP) algorithm, for example, have often been used because of its numerical robustness but standard implementations exhibit poor parallel performance. On the other hand, some methods trade stability for performance on parallel architectures such as the supernode Bunch--Kaufman used in the PARDISO solver. In this case, however, the factors obtained might not be used to accurately compute the solution of the system. For this reason we have designed a task-based LDLT factorization algorithm based on a new pivoting strategy called a posteriori threshold pivoting (APTP) that is much more suitable for modern multicore architectures and has the same numerical robustness as the TPP strategy. We implemented our algorithm in a new version of the SPRAL sparse symmetric indefinite direct solver, which initially supported GPU-only factorization. We have used OpenMP 4 task features to implement a multifrontal algorithm with dense factorizations using the novel APTP, and we show that it performs favorably compared to the state-of-the-art solvers HSL MA86, HSL MA97 and PARDISO both in terms of performance on a multicore machine and in terms of numerical robustness. Finally we show that this new solver is able to make use of GPU devices for accelerating the factorization on heterogeneous architectures. [ABSTRACT FROM AUTHOR]

With the semi-conductor technology gradually approaching its physical and heat limits, recent supercomputers have adopted major architectural changes to continue increasing the performance through more power-efficient heterogeneous many-core systems. Examples include Sunway TaihuLight that has four Management Processing Element (MPE) and 256 Computing Processing Element (CPE) inside one processor and Summit that has two central processing units (CPUs) and 6 graphics processing units (GPUs) inside one node. Meanwhile, current high-resolution Earth system models that desperately require more computing power, generally consist of millions of lines of legacy codes developed for traditional homogeneous multi-core processors and cannot automatically benefit from the advancement of supercomputer hardware. As a result, refactoring and optimizing the legacy models for new architectures become a key challenge along the road of taking advantage of greener and faster supercomputers, providing better support for the global climate research community and contributing to the long-lasting society task of addressing long-term climate change. This article reports the efforts of a large group in the International Laboratory for High-Resolution Earth System Prediction (iHESP) established by the cooperation of Qingdao Pilot National Laboratory for Marine Science and Technology (QNLM), Texas A & M University and the National Center for Atmospheric Research (NCAR), with the goal of enabling highly efficient simulations of the high-resolution (25-km atmosphere and 10-km ocean) Community Earth System Model (CESM-HR) on Sunway TaihuLight. The refactoring and optimizing efforts have improved the simulation speed of CESM-HR from 1 SYPD (simulation years per day) to 3.4 SYPD (with output disabled), and supported several hundred years of pre-industrial control simulations. With further strategies on deeper refactoring and optimizing for a few remaining computing hot spots, we expect an equivalent or even better efficiency than homogeneous CPU platforms. The refactoring and optimizing processes detailed in this paper on the Sunway system should have implications to similar efforts on other heterogeneous many-core systems such as GPU-based high-performance computing (HPC) systems. [ABSTRACT FROM AUTHOR]

Graphics processing unit (GPU)-based computing for climate system models is a longstanding research area of interest. The rapid radiative transfer model for general circulation models (RRTMG), a popular atmospheric radiative transfer model, can calculate atmospheric radiative fluxes and heating rates. However, the RRTMG has a high calculation time, so it is urgent to study its GPU-based efficient acceleration algorithm to enable large-scale and long-term climatic simulations. To improve the calculative efficiency of radiation transfer, this paper proposes a GPU-based acceleration algorithm for the RRTMG longwave radiation scheme (RRTMG_LW). The algorithm concept is accelerating the RRTMG_LW in the g-point dimension. After implementing the algorithm in CUDA Fortran, the G-RRTMG_LW was developed. The experimental results indicated that the algorithm was effective. In the case without I/O transfer, the G-RRTMG_LWon one K40 GPU obtained a speedup of 30.98x over the baseline performance on one single Intel Xeon E5-2680 CPU core. When compared to its counterpart running on 10 CPU cores of an Intel Xeon E5-2680 v2, the G-RRTMG_LW on one K20 GPU in the case without I/O transfer achieved a speedup of 2.35x. [ABSTRACT FROM AUTHOR]

Sparse matrix–vector multiplication (SpMV) kernel dominates the computing cost in numerous applications. Most of the existing studies dedicated to improving this kernel have been targeting just one type of processing units, mainly multicore CPUs or graphics processing units (GPUs), and have not explored the potential of the recent, rapidly emerging, CPU-GPU heterogeneous platforms. To take full advantage of these heterogeneous systems, the input sparse matrix has to be partitioned on different available processing units. The partitioning problem is more challenging with the existence of many sparse formats whose performances depend both on the sparsity of the input matrix and the used hardware. Thus, the best performance does not only depend on how to partition the input sparse matrix but also on which sparse format to use for each partition. To address this challenge, we propose in this article a new CPU-GPU heterogeneous method for computing the SpMV kernel that combines between different sparse formats to achieve better performance and better utilization of CPU-GPU heterogeneous platforms. The proposed solution horizontally partitions the input matrix into multiple block-rows and predicts their best sparse formats using machine learning-based performance models. A mapping algorithm is then used to assign the block-rows to the CPU and GPU(s) available in the system. Our experimental results using real-world large unstructured sparse matrices on two different machines show a noticeable performance improvement. [ABSTRACT FROM AUTHOR]

Virtual screening (VS) methods aid clinical research by predicting the interaction of ligands with pharmacological targets. The computational requirements of VS, along with the size of the databases, propitiate the use of high-performance computing. METADOCK is a tool for the application of metaheuristics to VS in heterogeneous clusters of computers based on central processing unit (CPU) and graphics processing unit (GPU). HYPERDOCK represents a step forward; the exploration for satisfactory metaheuristics is systematically approached by means of hyperheuristics working on top of the metaheuristic schema of METADOCK. Multiple metaheuristics are explored, so the process is computationally demanding. HYPERDOCK exploits the parallelism of METADOCK and includes parallelism at its own level. The different levels of parallelism can be used to exploit the parallelism offered by computational systems composed of multicore CPU + multi-GPUs. The efficient exploitation of these systems enables HYPERDOCK to improve ligand–receptor binding. [ABSTRACT FROM AUTHOR]

Genome-Wide Association Studies (GWASs), analyses that try to find a link between a given phenotype (such as a disease) and genetic markers, have been growing in popularity in the recent years. Relations between phenotypes and genotypes are not easy to identify, as most of the phenotypes are a product of the interaction between multiple genes, a phenomenon known as epistasis. Many authors have resorted to different approaches and hardware architectures in order to mitigate the exponential time complexity of the problem. However, these studies make some compromises in order to keep a reasonable execution time, such as limiting the number of genetic markers involved in the interaction, or discarding some of these markers in an initial filtering stage. This work presents MPI3SNP, a tool that implements a three-way exhaustive search for cluster architectures with the aim of mitigating the exponential growth of the run-time. Modern cluster solutions usually incorporate GPUs. Thus, MPI3SNP includes implementations for both multi-CPU and multi-GPU clusters. To contextualize the performance achieved, MPI3SNP is able to analyze an input of 6300 genetic markers and 3200 samples in less than 6 min using 768 CPU cores or 4 min using 8 NVIDIA K80 GPUs. The source code is available at https://github.com/chponte/mpi3snp. [ABSTRACT FROM AUTHOR]

This article introduces a novel semisupervised automated segmentation approach for breast magnetic resonance (MR) image on multicore CPU‐GPU systems. The basic idea of the proposed method is clustering‐based semisupervised classifier devised by elliptical gamma mixture model (EGMM). Parameters of EGMM are identified by the iterative log‐expectation maximization (EM) algorithm. The suggested classifier labels the groups of voxels in an input image first and then classifies the image slices using the EGMM. Two different implementations of the proposed algorithm have been developed based on two different types of high‐performance computing architectures such as graphics processing units (GPUs) and multicore processors. To realize the real‐time segmentation performance of our algorithm with two distinctive architecture, we have tested a set of breast MR images collected from MedPix. Comparison between two architectures in terms of segmentation performance and computational cost is assessed by the analysis of simulation and experimental results. [ABSTRACT FROM AUTHOR]

A block-inverse preconditioner (BIP) is proposed to accelerate solving implicit time integration in the context of Newton–Krylov approach used in micromagnetic simulations for solving the Landau–Lifshitz–Gilbert equation. A coefficient matrix is generated and stored for the linear system of Newton method. BIP is formulated by subdividing the coefficient matrix into small blocks and directly inverting them. The cost of preconditioning is low since inverting and multiplying small blocks is fast, which can be further minimized by parallel computing on multicore CPUs or GPUs. The effectiveness, speed, robustness, and scalability of BIP is demonstrated by numerical simulation experiments. Comparisons to incomplete LU preconditioning methods are conducted to demonstrate the effectiveness of BIP. [ABSTRACT FROM AUTHOR]

In the last decades, the problem of target detection has received considerable attention in remote sensing applications. When this problem is tackled using hyperspectral images with hundreds of bands, the use of high-performance computing (HPC) is essential. One of the most popular algorithms in the hyperspectral image analysis community for this purpose is the automatic target detection and classification algorithm (ATDCA). Previous research has already investigated the mapping of ATDCA on HPC platforms such as multicore processors, graphics processing units (GPUs), and field-programmable gate arrays (FPGAs), showing impressive speedup factors (after careful fine-tuning) that allow for its exploitation in time-critical scenarios. However, the lack of standardization resulted in most implementations being too specific to a given architecture, eliminating (or at least making extremely difficult) code reusability across different platforms. In order to address this issue, we present a portability study of an implementation of ATDCA developed using the open computing language (OpenCL). We focus on cross-platform parameters such as performance, energy consumption, and code design complexity, as compared to previously developed (hand-tuned) implementations. Our portability study analyzes different strategies to expose data parallelism as well as enable the efficient exploitation of complex memory hierarchies in heterogeneous devices. We also conduct an assessment of energy consumption and discuss metrics to analyze the quality of our code. The conducted experiments—using synthetic and real hyperspectral data sets collected by the Hyperspectral Digital Imagery Collection Experiment (HYDICE) and NASA’s Airborne Visible Infra-Red Imaging Spectrometer (AVIRIS)—demonstrate, for the first time in the literature, that portability across different HPC platforms can be achieved for real-time target detection in hyperspectral missions. [ABSTRACT FROM AUTHOR]

Sketches are being extensively used in a large number of real world applications to estimate frequencies of data items. Due to the unprecedented increase in the amount of Internet data and a relatively slower increase in the size of on-chip memories, existing sketches are becoming increasingly unable to keep the accuracy of the frequency estimates at an acceptable level. In this paper, we design a new sketch, called FID-sketch, that has a significantly higher accuracy and a much smaller on-chip memory footprint compared to the existing sketches. The key intuition behind the design of the FID-sketch is that before inserting an item, unlike prior sketches, it first estimates the current value of the frequency of that item stored in the sketch, and then increments as few counters as possible instead of incrementing a pre-determined fixed number of counters. We carried out extensive experiments to evaluate and compare the performance of FID-sketch with existing sketches on multi-core CPU and GPU platforms. Our experimental results show that our FID-sketch significantly outperforms the state-of-the-art with 36.7 times lower relative error. We have released the source code of our proposed sketch and other related sketches that we implemented at Github [21]. [ABSTRACT FROM AUTHOR]

Due to decelerating gains in single-core CPU performance, computationally expensive simulations are increasingly executed on highly parallel hardware platforms. Agent-based simulations, where simulated entities act with a certain degree of autonomy, frequently provide ample opportunities for parallelisation. Thus, a vast variety of approaches proposed in the literature demonstrated considerable performance gains using hardware platforms such as many-core CPUs and GPUs, merged CPU-GPU chips as well as Field Programmable Gate Arrays. Typically, a combination of techniques is required to achieve high performance for a given simulation model, putting substantial burden onmodellers. To the best of our knowledge, no systematic overview of techniques for agent-based simulations on hardware accelerators has been given in the literature. To close this gap, we provide an overview and categorisation of the literature according to the applied techniques. Since, at the current state of research, challenges such as the partitioning of amodel for execution on heterogeneous hardware are still addressed in a largely manual process, we sketch directions for future research towards automating the hardware mapping and execution. This survey targets modellers seeking an overview of suitable hardware platforms and execution techniques for a specific simulation model, as well as methodology researchers interested in potential research gaps requiring further exploration. [ABSTRACT FROM AUTHOR]