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Gene co-expression networks are valuable tools for discovering biologically relevant information within gene expression data. However, analysing large datasets presents challenges due to the identification of nonlinear gene–gene associations and the need to process an ever-growing number of gene pairs and their potential network connections. These challenges mean that some experiments are discarded because the techniques do not support these intense workloads. This paper presents pyEnGNet, a Python library that can generate gene co-expression networks in High-performance computing environments. To do this, pyEnGNet harnesses CPU and multi-GPU parallel computing resources, efficiently handling large datasets. These implementations have optimised memory management and processing, delivering timely results. We have used synthetic datasets to prove the runtime and intensive workload improvements. In addition, pyEnGNet was used in a real-life study of patients after allogeneic stem cell transplantation with invasive aspergillosis and was able to detect biological perspectives in the study. [ABSTRACT FROM AUTHOR]

Top-K and selection operations are critical in data processing and analysis, and their efficient implementation on GPUs is increasingly important due to the growing demands of data analysis. Existing methods, primarily relying on the bucket partition execution model, encounter challenges such as uneven bucket distribution and latency in merging processes. To address these issues, we introduce a novel Split-Bucket Partition (SBP) execution model that specifically addresses these challenges. Additionally, we propose task and control flow optimizations targeted at top-K and selection algorithms, which further contribute to performance improvements. Our optimized algorithms significantly outperform existing approaches, delivering performance gains of up to 2.3 times and 1.6 times for different bucket partitioning rules. Our algorithms show robust performance improvements in non-uniform data scenarios, with gains ranging from 1.9 times to 15.5 times. However, it should be noted that the SBP model has limitations related to shared memory and register utilization, potentially impacting performance. Tests on TU102 and A100 GPU architectures validate the effectiveness of our approach, achieving a maximum speedup of 2.9 times. The study suggests that while the SBP model is effective for top-K and selection algorithms, it also holds promise for other computational tasks, setting the stage for future research. [ABSTRACT FROM AUTHOR]

Efficient computation of the geopotential gradient is essential for numerical propagators, particularly in scenarios involving low Earth orbits. Conventional geopotential calculations are based on spherical harmonics series, which become computationally demanding as the degree/order increases. This computational burden can be mitigated by means of parallelized algorithms. Additionally, certain situations lend themselves to high parallelization, such as the propagation of space debris catalogs, satellite mega-constellations, or the dispersion of particles resulting from a space collision event. This paper introduces an optimized Graphics Processing Unit (GPU) implementation designed to facilitate extensive parallelization in the geopotential gradient calculation. The formulation developed in this study is not specific to any GPU. However, to illustrate the low-level optimizations necessary for an efficient implementation, we selected the Compute Unified Device Architecture (CUDA) as the dominant and de facto standard in parallel computing. Nevertheless, most of the concepts and optimizations presented in this paper are also valid for other GPU architectures. Built upon the spherical harmonic expansion using the Cunningham formulation, which is well-suited for GPU computations, our implementation offers several variants with different tradeoffs between speed and accuracy. Besides GPU double precision, we introduced a mixed precision arithmetic –a hybrid between single and double precision– that exploits GPU capabilities with a low penalty in accuracy. The proposed algorithm was implemented as a software reusable module, and its performance was evaluated against GMAT, GODOT, and Orekit astrodynamic codes. The algorithm's accuracy in double precision is comparable to such codes. The mixed precision version showed enough accuracy for LEO satellite propagation, with around 1 m difference in four days. Testing across different CUDA architectures revealed very high speed-up factors compared to a single CPU, reaching a speed-up of 645 for the mixed precision variant and 450 for the double precision one in the propagation of about 3200 objects with a geopotential of degree/order 126 × 126 using an A100 GPU device. [ABSTRACT FROM AUTHOR]

FlowDenoising is a new approach to noise reduction in biological volumes obtained with three-dimensional electron microscopy (3DEM). Its abilities to enhance the structural features stem from the fact that an anisotropic Gaussian filtering is steered according to the local structures. To this end, the Optical Flow (OF) among consecutive slices is estimated, which is the most computationally expensive step in this approach. In this article, a hybrid CPU/GPU implementation of FlowDenoising is introduced and evaluated. It exploits parallel computing by distributing the workload among multiple cores and takes advantage of the massive processing in GPUs to accelerate the OF estimation. The hybrid implementation provides remarkable speed-up factors and an important reduction of the processing time, which is particularly relevant for the denoising of huge volumes typically found in 3DEM. [ABSTRACT FROM AUTHOR]

This paper presents a dynamic-phasor-based, average-value modeling method for power systems with extensive converter-tied subsystems. In the proposed approach, the overall system model is constructed using modular functions, interfacing both conventional and converter-tied resources. Model validation is performed against detailed Electro-Magnetic Transient (EMT) simulations. The analytical capabilities offered by the proposed modeling method are demonstrated on a modified IEEE 9-bus system. A Graphics Processing Unit (GPU)-based parallel computing approach for the solution of the resulting model is presented and exemplified on a modified IEEE 118-bus system, showing significant improvements in computing efficiency over EMT solvers. A co-simulation approach using a Central Processing Unit (CPU) and a GPU is also presented and exemplified using a modified version of the IEEE 118-bus system, demonstrating the model's parallelization. [ABSTRACT FROM AUTHOR]

Virtual screening is an early stage in the drug discovery process that selects the most promising candidates. In the urgent computing scenario, finding a solution in the shortest time frame is critical. Any improvement in the performance of a virtual screening application translates into an increase in the number of candidates evaluated, thereby raising the probability of finding a drug. In this paper, we show how we can improve application throughput using Out-of-kernel optimizations. They use input features, kernel requirements, and architectural features to rearrange the kernel inputs, executing them out of order, to improve the computation efficiency. These optimizations' implementations are designed on an extreme-scale virtual screening application, named LiGen, that can hinge on CUDA and SYCL kernels to carry out the computation on modern supercomputer nodes. Even if they are tailored to a single application, they might also be of interest for applications that share a similar design pattern. The experimental results show how these optimizations can increase kernel performance by 2 × , respectively, up to 2.2 × in CUDA and up to 1.9 × , in SYCL. Moreover, the reported speedup can be achieved with the best-proposed parameterization, as shown by the data we collected and reported in this manuscript. [ABSTRACT FROM AUTHOR]

This study focuses on the implementation of the spectral difference (SD) method on hexahedral elements to NVIDIA graphics processing units (GPUs) using the Compute Unified Device Architecture (CUDA) for aeroacoustic problems. Three problems were addressed in the implementation of this study: thread parallelism strategy optimization within the GPU, data access patterns management, and multi-GPU parallelization implementation. Computational speed testing showed that the three factors significantly affect the efficiency of the code on the GPU. The implemented GPU solver was validated using an inviscid problem and a viscous problem. The numerical results show that the GPU solver achieves the same level of accuracy as the CPU program, with remarkable speed improvements. Specifically, compared with a single CPU core with a turbo boost frequency of 3.2 GHz (Intel Xeon Silver 4210), the inviscid case tested on an RTX 2070 Super GPU achieved acceleration of 122.4× , and the viscous case conducted on an RTX 3090 GPU achieved acceleration of 229.7×. Additionally, the GPU solver exhibits a parallel efficiency exceeding 93% when performing parallel computing on a platform with multiple RTX 3090 GPU cards. Furthermore, the GPU-accelerated computational aeroacoustics solver was applied to compute the noise from a low-speed propeller. The computed results were compared with experimental data, and the excellent agreement demonstrated the effectiveness and feasibility of the GPU implementation of the SD solver. [ABSTRACT FROM AUTHOR]

Electric vehicles (EVs) are becoming more and more popular as they provide significant environmental benefits compared to fossil-fuel vehicles. However, they represent substantial loads on the power grid, and the scheduling of EV charging can be a challenge, especially in large parking lots. This paper presents a metaheuristic-based approach parallelized on multicore processors (CPU) and graphics processing units (GPU) to optimize the scheduling of EV charging in a single smart parking lot. The proposed method uses a particle swarm optimization algorithm that takes as input the arrival time, the departure time, and the power demand of the vehicles and produces an optimized charging schedule for all vehicles in the parking lot, which minimizes the overall charging cost while respecting the chargers' capacity and the parking lot feeder capacity. The algorithm exploits task-level parallelism for the multicore CPU implementation and data-level parallelism for the GPU implementation. The proposed algorithm is tested in simulation on parking lots containing 20 to 500 EVs. The parallel implementation on CPUs provides a speedup of 7.1x, while the implementation on a GPU provides a speedup of up to 247.6x. The parallel implementation on a GPU is able to optimize the charging schedule for a 20-EV parking lot in 0.87 s and a 500-EV lot in just under 30 s. These runtimes allow for real-time computation when a vehicle arrives at the parking lot or when the electricity cost profile changes. [ABSTRACT FROM AUTHOR]

The moving particle simulation (MPS) method is a simulation technique capable of calculating free surface and incompressible flows. As a particle-based method, MPS requires significant computational resources when simulating flow in a large-scale domain with a huge number of particles. Therefore, improving computational speed is a crucial aspect of current research in particle methods. In recent decades, many-core CPUs and GPUs have been widely utilized in scientific simulations to significantly enhance computational efficiency. However, the implementation of MPS on different types of hardware is not a trivial task. In this study, we present an implementation method for the explicit MPS that utilizes the Taichi parallel programming language. When it comes to CPU computing, Taichi's computational efficiency is comparable to that of OpenMP. Nevertheless, when GPU computing is utilized, the acceleration of Taichi in parallel computing is not as fast as the CUDA implementation. Our developed explicit MPS solver demonstrates significant performance improvements in simulating dam-break flow dynamics. [ABSTRACT FROM AUTHOR]

Point-in-spherical-polygon tests are a fundamental problem in computational geometry. For such tests, efficiency is much required for many global information processing matters, especially their real-time processing. Though many efforts have been made, it is still challenging due to the constraints from the non-Euclidean space of the sphere. Recently, a method is proposed to construct an Adaptive Hexagonal Hierarchical Grid (AHHG) to manage spherical polygon edges, by which the non-Euclidean space constraint of the sphere can be well handled to improve point-in-spherical-polygon tests. However, this method is very expensive in the construction of AHHGs, which prevents its use in practice. In this paper, we present novel measures to divide the task of AHHG construction into several subtasks to solve the problems that arise in the parallel construction of incongruent adaptive hierarchies, so we can exploit the parallel computing potential of GPUs for acceleration. We also develop measures to adaptively optimize the hierarchical levels of an AHHG for high efficiency. Experimental results show that we can answer 1,000,000 query points against dynamically varying spherical polygons in over 100,000 edges in real time on a personnel computer, where AHHGs for spherical polygons are individually constructed. This is much superior to the existing methods. [ABSTRACT FROM AUTHOR]

This paper deals with an industrial problem of machining line design, which consists in partitioning a given set of operations into several subsets corresponding to workstations and sequencing the operations to satisfy the technical requirements and achieve the best performance of the line. The problem has a complex set of constraints that include partial order on operations, part positioning, inclusion, exclusion, cycle time, and installation of parallel machines on a workstation. The problem is NP-hard and even finding a feasible solution can be a difficult task from the practical point of view. A parallel evolutionary algorithm (EA) is proposed and implemented for execution on a Graphics Processing Unit (GPU). The parallelization in the EA is done by working on several parents in one iteration and in multiple application of mutation operator to the same parent to produce the best offspring. The proposed approach is evaluated on large scale instances and demonstrated superior performance compared to the algorithms from the literature in terms of running time and ability to obtain feasible solutions. It is shown that in comparison to the traditional populational EA scheme the newly proposed algorithm is more suitable for advanced GPUs with a large number of cores. [ABSTRACT FROM AUTHOR]

Heterogeneous architectures consisting of both central processing units and graphics processing units are common in contemporary computer systems. For that reason, several programming models have been developed to exploit available parallelism, such as low-level CUDA and OpenCL, and directive-based OpenMP and OpenACC. In this paper we explore and evaluate the applicability of OpenACC, which is a directive-based programming model for GPUs. We focus both on the performance and programming effort needed to parallelize the existing sequential algorithms for GPU execution. The evaluation is based on the benchmark suite Parboil, which consists of 11 different mini-applications from different scientific domains, both compute- and memory-bound. The results show that mini-apps parallelized with OpenACC can achieve significant speedups over sequential implementations and in some cases, even outperform CUDA implementations. Furthermore, there is less of a programming effort compared to low-level models, such as CUDA and OpenCL, because a majority of the work is left to the compiler and overall, the code needs less restructuring. [ABSTRACT FROM AUTHOR]

As the development of high-performance computing (HPC) is growing, exascale computing is on the horizon. Therefore, it is imperative to develop parallel systems, such as graphics processing units (GPUs) and programming models, that can effectively utilise the powerful processing resources of exascale computing. A tri-level programming model comprising message passing interface (MPI), compute unified device architecture (CUDA), and open multi-processing (OpenMP) models may significantly enhance the parallelism, performance, productivity, and programmability of the heterogeneous architecture. However, the use of multiple programming models often leads to unexpected errors and behaviours during run-time. It is also difficult to detect such errors in high-level parallel programming languages. Therefore, this present study proposes a parallel hybrid testing tool that employs both static and dynamic testing techniques to address this issue. The proposed tool was designed to identify the run-time errors of C++ and MPI + OpenMP + CUDA systems by analysing the source code during run-time, thereby optimising the testing process and ensuring comprehensive error detection. The proposed tool was able to identify and categorise the run-time errors of tri-level programming models. This highlights the need for a parallel testing tool that is specifically designed for tri-level MPI + OpenMP + CUDA programming models. As contemporary parallel testing tools cannot, at present, be used to test software applications produced using tri-level MPI + OpenMP + CUDA programming models, this present study proposes the architecture of a parallel testing tool to detect run-time errors in tri-level MPI + OpenMP + CUDA programming models. [ABSTRACT FROM AUTHOR]

With the development of engineering technology, engineering has higher requirements for the accuracy and the scale of simulation calculation. The computational efficiency of traditional serial programs cannot meet the requirements of engineering. Therefore, reducing the calculation time of the temperature control simulation program has important engineering significance for real-time simulation of temperature field and stress field, and then adopting more reasonable temperature control and crack prevention measures. GPU parallel computing is introduced into the temperature control simulation program of massive concrete to solve this problem and the optimization is carried out. Considering factors such as GPU clock rate, number of cores, parallel overhead and Parallel Region, the improved GPU parallel algorithm analysis indicator formula is proposed. It makes up for the shortcomings of traditional formulas that focus only on time. According to this formula, when there are enough threads, the parallel effect is limited by the size of the parallel domain, and when the parallel domain is large enough, the efficiency is limited by the parallel overhead and the clock rate. This paper studies the optimal Kernel execution configuration. Shared memory is utilized to improve memory access efficiency by 155%. After solving the problem of bank conflicts, an accelerate rate of 437.5× was realized in the subroutine of the matrix transpose of the solver. The asynchronous parallel of data access and logical operation is realized on GPU by using CUDA Stream, which can overlap part of the data access time. On the basis of GPU parallelism, asynchronous parallelism can double the computing efficiency. Compared with the serial program, the accelerate rate of inner product matrix multiplication of the GPU asynchronous parallel program is 61.42×. This study further proposed a theoretical formula of data access overlap rate to guide the selection of the number of CUDA streams to achieve the optimal computing conditions. The GPU parallel program compiled and optimized by the CUDA Fortran platform can effectively improve the computational efficiency of the simulation program for concrete temperature control, and better serve engineering computing. [ABSTRACT FROM AUTHOR]

Context. Autonomous vehicles are becoming increasingly popular, and one of the important modern challenges in their development is ensuring their effective navigation in space and movement within designated lanes. This paper examines a method of spatial orientation for vehicles using computer vision and artificial neural networks. The research focused on the navigation system of an autonomous vehicle, which incorporates the use of modern distributed and parallel computing technologies. Objective. The aim of this work is to enhance modern autonomous vehicle navigation algorithms through parallel training of artificial neural networks and to determine the optimal combination of technologies and nodes of devices to increase speed and enable real-time decision-making capabilities in spatial navigation for autonomous vehicles. Method. The research establishes that the utilization of computer vision and neural networks for road lane segmentation proves to be an effective method for spatial orientation of autonomous vehicles. For multi-core computing systems, the application of parallel programming technology, OpenMP, for neural network training on processors with varying numbers of parallel threads increases the algorithm's execution speed. However, the use of CUDA technology for neural network training on a graphics processing unit significantly enhances prediction speeds compared to OpenMP. Additionally, the feasibility of employing PyTorch Distributed Data Parallel (DDP) technology for training the neural network across multiple graphics processing units (nodes) simultaneously was explored. This approach further improved prediction execution times compared to using a single graphics processing unit. Results. An algorithm for training and prediction of an artificial neural network was developed using two independent nodes, each equipped with separate graphics processing units, and their synchronization for exchanging training results after each epoch, employing PyTorch Distributed Data Parallel (DDP) technology. This approach allows for scalable computations across a higher number of resources, significantly expediting the model training process. Conclusions. The conducted experiments have affirmed the effectiveness of the proposed algorithm, warranting the recommendation of this research for further advancement in autonomous vehicles and enhancement of their navigational capabilities. Notably, the research outcomes can find applications in various domains, encompassing automotive manufacturing, logistics, and urban transportation infrastructure. The obtained results are expected to assist future researchers in understanding the most efficient hardware and software resources to employ for implementing AI-based navigation systems in autonomous vehicles. Prospects for future investigations may encompass refining the accuracy of the proposed parallel algorithm without compromising its efficiency metrics. Furthermore, there is potential for experimental exploration of the proposed algorithm in more intricate practical scenarios of diverse nature and dimensions. [ABSTRACT FROM AUTHOR]

An overview of the results obtained within the algebra of algorithms and tools for the automated development of programs for multiprocessor platforms is presented. Algorithmics is based on the theory of algorithmic algebras and is focused on solving a wide range of applied problems and developing software tools for automated design and synthesis of classes of algorithms and programs. The generality of algorithms is based on the variety of interpretations of algorithm schemes and provides the possibility of applying algorithms and their tools for solving problems related to various subject domains. The combination of algorithmics and rule rewriting technique made it possible to develop methods and tools aimed at automated design, transformation, synthesis, and tuning of programs for various platforms (multicore processors, graphics processing units, and field-programmable gate arrays). [ABSTRACT FROM AUTHOR]

The BEAVRS benchmark is solved by PRAGMA, the graphics processing unit (GPU)–based continuous-energy Monte Carlo code. The solutions consist of the detailed simulation results for the two cycles that involve the reactivity and pin power distribution information for the zero-power physics tests and depletion. Primary results at hot zero power, such as the critical boron concentration at various rodded conditions, control rod bank worth, isothermal temperature coefficients, and assemblywise detector signal, are compared with the measured data. Core-follow calculations are performed with varied power, and the resulting boron letdown curves are compared with the measured one. Hot full-power depletion is also performed and the resulting pinwise power distributions of cycle 1 are compared with the nTRACER results. The comparison with the measured data and also with the nTRACER results demonstrates the high solution fidelity of PRAGMA. In all the calculations, PRAGMA uses a tremendously large number of histories, ranging from up to hundreds of millions per cycle, that are used to fully exploit the massive parallel computing capacity of GPUs. The execution time of the entire core-follow calculation with about 30 burnup steps takes less than 16 h on a single rack of computing nodes mounted with 24 gaming GPUs, which represents considerably high Monte Carlo core calculation performance. [ABSTRACT FROM AUTHOR]

We propose a polylithic method for medium-term scheduling of a large-scale industrial plant operating in a continuous mode. The method combines a decomposition approach, a genetic algorithm (GA) and a constructive MILP-based heuristic. In the decomposition, decisions are made at two levels, using the rolling horizon approach. At the upper level, a reduced set of products and the time period is chosen to be considered in the lower level. At the lower level, a short-term scheduling MILP-model with event-based representation is used. A heuristic solution to the lower level problem is found using a constructive Moving Window heuristic guided by a genetic algorithm. The GA is applied for finding efficient utilisation of critical units in the lower level problem. For solving the one unit scheduling problem, a parallel dynamic programming algorithm is proposed. Implementation of the dynamic programming algorithm for a graphics processing unit (GPU) is incorporated in the GA for improving its performance. The experimental study of the proposed method on a real case of a large-scale plant shows a significant improvement of the solution quality and the solving time comparing to the pure decomposition algorithm proposed in the earlier study, and confirmed suitability of the proposed approach for the real-life production scheduling. In particular, the reduction of the number of changeovers and their duration in the obtained solution as well as the CPU time of solving the problem was about 60% using the new approach. [ABSTRACT FROM AUTHOR]

Nowadays, almost all network traffic is encrypted. Attackers hide themselves using this traffic and attack over encrypted channels. Inspections performed only on packet headers and metadata are insufficient for detecting cyberattacks over encrypted channels. Therefore, it is important to analyze packet contents in applications that require control over payloads, such as content filtering, intrusion detection systems (IDSs), data loss prevention systems (DLPs), and fraud detection. This technology, known as deep packet inspection (DPI), provides full control over the communication between two end stations by keenly analyzing the network traffic. This study proposes a multi-pattern-matching algorithm that reduces the memory space and time required in the DPI pattern matching compared to traditional automaton-based algorithms with its ability to process more than one packet payload character at once. The pattern-matching process in the DPI system created to evaluate the performance of the proposed algorithm (PA) is conducted on the graphics processing unit (GPU), which accelerates the processing of network packets with its parallel computing capability. This study compares the PA with the Aho-Corasick (AC) and Wu–Manber (WM) algorithms, which are widely used in the pattern-matching process, considering the memory space required and throughput obtained. Algorithm tables created with a dataset containing 500 patterns use 425 and 688 times less memory space than those of the AC and WM algorithms, respectively. In the pattern-matching process using these tables, the PA is 3.5 and 1.5 times more efficient than the AC and WM algorithms, respectively. [ABSTRACT FROM AUTHOR]

Advances in the graphics processing unit (GPU) development led to the opportunity for software developers to increase the execution speed for their programs by massive parallelization of the algorithms using GPU programming. NVIDIA company developed an arhitecture for parallel computing named Compute Unified Device Architecture (CUDA) which includes a set of CUDA instructions and the hardware for parallel computing. Computational Physics is an interdisciplinary field which is in continuous progress and which studies, develops and optimizes numerical algorithms and computational techniques for their application in solving various physics problems. Computational Physics has applicability in all sub-branches of physics and related fields such as: biophysics, astrophysics, plasma physics, biomechanics, fluid physics, etc. Moreover, with the evolution of technology in the last few decades, this relatively new field has helped to quickly obtain results in these fields, facilitating the connection between theoretical and experimental physics. In this paper, some of the latest researches and results obtained in computational physics by using GPU computing with CUDA architecture are reviewed. [ABSTRACT FROM AUTHOR]

Iterative stencil computations are widely used in numerical simulations. They present a high degree of parallelism, high locality and mostly-coalesced memory access patterns. Therefore, GPUs are good candidates to speed up their computation. However, the development of stencil programs that can work with huge grids in distributed systems with multiple GPUs is not straightforward, since it requires solving problems related to the partition of the grid across nodes and devices, and the synchronization and data movement across remote GPUs. In this work, we present EPSILOD, a high-productivity parallel programming skeleton for iterative stencil computations on distributed multi-GPUs, of the same or different vendors that supports any type of n-dimensional geometric stencils of any order. It uses an abstract specification of the stencil pattern (neighbors and weights) to internally derive the data partition, synchronizations and communications. Computation is split to better overlap with communications. This paper describes the underlying architecture of EPSILOD, its main components, and presents an experimental evaluation to show the benefits of our approach, including a comparison with another state-of-the-art solution. The experimental results show that EPSILOD is faster and shows good strong and weak scalability for platforms with both homogeneous and heterogeneous types of GPU. [ABSTRACT FROM AUTHOR]

The growing number of space objects leads to increases in the potential risks of damage to satellites and generates space debris after colliding. Conjunction assessment analysis is the one of keys to evaluating the collision risk of satellites and satellite operators require the analyzed results as fast as possible to decide and execute collision maneuver planning. However, the computation time to analyze the potential risk of all satellites is proportional to the number of space objects. The conjunction filters and parallel computing techniques can shorten the computation cost of conjunction analysis to provide the analyzed results. Therefore, this paper shows the investigation of the conjunction filter performances (accuracy and computation speed): Smart Sieve, CSieve and CAOS-D (combination of both Smart Sieve and CSieve) in both a single satellite (one vs. all) and all space objects (all vs. all) cases. Then, all the screening filters are developed to implement an algorithm that executes General-purpose computing on graphics processing units (GPGPU) by using NVIDIAs Compute Unified Device Architecture (CUDA). The analyzed results show the comparison results of the accuracy of conjunction screening analysis and computation times of each filter when implemented with the parallel computation techniques. [ABSTRACT FROM AUTHOR]

In this study, a multi-phase-field (MPF) framework for predicting epitaxial grain growth in selective laser melting (SLM) additive manufacturing (AM) with multi-track and multi-layer scanning was developed. The spatiotemporal change in temperature was approximated using the Rosenthal equation, which provides a theoretical solution for the temperature distribution due to a moving point heat source. The powder bed was modeled as a polycrystalline layer. Large-scale MPF simulations for SLM-AM were performed using parallel computing with multiple graphics processing units. Using the MPF framework developed herein, we simulated SLM-AM with four tracks and four layers for 316L stainless steel. By observing the epitaxial grain growth process on two-dimensional cross-sections and in three dimensions, we clarified a typical growth procedure of grains with characteristic 3D shapes. The MPF framework will potentially enable a systematic estimation of the material microstructures formed during SLM-AM. [ABSTRACT FROM AUTHOR]

Summary: The Floyd‐Warshall algorithm is a well‐known algorithm to compute the distance of all pairs of nodes of a graph. The Blocked Floyd‐Warshall algorithm, a variant of the Floyd‐Warshall has been proposed to accelerate the Floyd‐Warshall algorithm by means of a graphics processing unit (GPU) architecture. The previously published GPU implementations for the Blocked Floyd‐Warshall algorithm perform many separated kernel calls for costly barrier synchronization. The main contribution of this article is to present efficient implementations of the Blocked Floyd‐Warshall algorithm, which performs no barrier synchronization and invokes only one kernel call. Experimental results using NVIDIA Tesla V100 show that our implementation runs 1.05‐1.31 times faster than the previously published one. Our implementation with SIMD functions also runs 1.00‐1.28 times faster than it. Second, we propose efficient GPU implementations to execute the Blocked Floyd‐Warshall algorithm for many graphs at the same time. From the experimental results, our single kernel implementation runs 1.03‐1.60 times faster than multiple kernel one. In terms of implementations with SIMD functions, our single kernel implementation runs 1.01‐1.89 times faster than it. We also propose the low‐latency implementations for many graphs. Finally, we implemented the parallel Floyd‐Warshall algorithm on the multicore processors. [ABSTRACT FROM AUTHOR]

The energy consumption of Information and Communications Technology (ICT) presents a new grand technological challenge. The two main approaches to tackle the challenge include the development of energy-efficient hardware and software. The development of energy-efficient software employing application-level energy optimization techniques has become an important category owing to the paradigm shift in the composition of digital platforms from single-core processors to heterogeneous platforms integrating multicore CPUs and graphics processing units (GPUs). In this work, we present an overview of application-level bi-objective optimization methods for energy and performance that address two fundamental challenges, non-linearity and heterogeneity, inherent in modern high-performance computing (HPC) platforms. Applying the methods requires energy profiles of the application's computational kernels executing on the different compute devices of the HPC platform. Therefore, we summarize the research innovations in the three mainstream component-level energy measurement methods and present their accuracy and performance tradeoffs. Finally, scaling the optimization methods for energy and performance is crucial to achieving energy efficiency objectives and meeting quality-of-service requirements in modern HPC platforms and cloud computing infrastructures. We introduce the building blocks needed to achieve this scaling and conclude with the challenges to scaling. Briefly, two significant challenges are described, namely fast optimization methods and accurate component-level energy runtime measurements, especially for components running on accelerators. [ABSTRACT FROM AUTHOR]

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The need for increased application performance in high-integrity systems such as those in avionics is on the rise as software continues to implement more complex functionalities. The prevalent computing solution for future high-integrity embedded products is multi-processor systems-on-chip (MPSoC) processors. MPSoCs include central processing unit (CPU) multicores that enable improving performance via thread-level parallelism. MPSoCs also include generic accelerators (graphics processing units [GPUs]) and application-specific accelerators. However, the data processing approach (DPA) required to exploit each of these underlying parallel hardware blocks carries several open challenges to enable the safe deployment in high-integrity domains. The main challenges include the qualification of its associated runtime system and the difficulties in analyzing programs deploying the DPA with out-of-the-box timing analysis and code coverage tools. In this work, we perform a thorough analysis of vector extensions (VExts) in current commercial off-the-shelf (COTS) processors for high-integrity systems. We show that VExts prevent many of the challenges arising with parallel programming models and GPUs. Unlike other DPAs, VExts require no runtime support, prevent design race conditions that might arise with parallel programming models, and have minimum impact on the software ecosystem, enabling the use of existing code coverage and timing analysis tools. We develop vectorized versions of neural network kernels and show that the NVIDIA Xavier VExts provide a reasonable increase in guaranteed application performance of up to 2.7x. Our analysis contends that VExts are the DPA approach with arguably the fastest path for adoption in high-integrity systems. [ABSTRACT FROM AUTHOR]

The manufacturing processes of unmanned aerial vehicle (UAV) power systems generate large amounts of data and knowledge. The extraction of useful information or patterns from redundant data and knowledge texts has become a challenge in intelligent manufacturing. Unfortunately, graphics processing unit (GPU)-based parallel computing is limited, and the inference speeds of the available named entity recognition (NER) models for Chinese text datasets are low because they are mainly based on the long short-term memory (LSTM) algorithm. Herein, first, the flat-lattice transformer (FLAT) model was optimized by using a stochastic gradient descent with momentum (SGDM) optimizer and adjusting the model hyperparameters. Compared with the existing NER methods, the proposed optimization algorithm achieved better performance on the available dataset. Then, an NER method named the TL_FLAT model based on transfer learning and the abovementioned optimization model was introduced. Finally, a Chinese text dataset from a UAV power system created by the authors was used to validate the proposed method. The F1 score was 76.26%, the precision value was 76.98%, and the recall value was 75.56%, indicating that the TL_FLAT model was suitable for Chinese text entity recognition for UAV power systems. [ABSTRACT FROM AUTHOR]

The range migration algorithm (RMA) based on Fourier transformation is widely applied in millimeter-wave (MMW) close-range imaging because of its few operations and small approximation. However, its interpolation stage is not effective due to the involved intensive logic controls, which limits the speed performance in a graphics processing unit (GPU) platform. Therefore, in this paper, we present an acceleration optimization method based on the hybrid GPU and central processing unit (CPU) parallel computation for implementing the RMA. The proposed method exploits the strong logic-control capability of the CPU to assist the GPU in processing the logic controls of the interpolation stage. The common positions of wavenumber-domain components to be interpolated are calculated by the CPU and stored in the constant memory for broadcast at any time. This avoids the repetitive computation consumed in a GPU-only scheme. Then the GPU is responsible for the remaining matrix-related steps and outputs the needed wavenumber-domain values. The imaging experiments verify the acceleration efficiency of the proposed method and demonstrate that the speedup ratio of our proposed method is more than 15 times of that by the CPU-only method, and more than 2 times of that by the GPU-only method. [ABSTRACT FROM AUTHOR]

Kernel density estimation (KDE) is a commonly used method for spatial point pattern analysis, but it is computationally demanding when analyzing large datasets. GPU-based parallel computing has been adopted to address such computational challenges. The existing GPU-parallel KDE method, however, utilizes only one GPU for parallel computing. Additionally, it assumes that the input data can be held in GPU memory all at once for computation, which is unrealistic when conducting KDE analysis over large geographic areas at high resolution. This study develops a multi-GPU-parallel and tile-based KDE algorithm to overcome these limitations. It exploits multiple GPUs to speedup complex KDE computation by distributing computation across GPUs, and approaches density estimation with a tile-based strategy to bypass the memory bottleneck. Experiment results show that the parallel KDE algorithm running on multiple GPUs achieves significant speedups over running on a single GPU, and higher speedups are achieved on KDE tasks of a larger problem size. The tile-based strategy renders it feasible to estimate high-resolution density surfaces over large areas even on GPUs with only limited memory. Multi-GPU parallel computing and tile-based density estimation, while incurring very little computational overhead, effectively enable conducting KDE for large-scale spatial point pattern analysis on geospatial big data. [ABSTRACT FROM AUTHOR]

This paper proposes an efficient and extensible simulation framework for mid‐fidelity wind field model based on heterogeneous architecture. The wind field model consists of 3‐D wind inflow, wake dynamics, and wind turbine models. The CPU‐GPU heterogeneous platform accelerates the 3‐D wind inflow model simulation by performing large‐scale parallel computing based on GPU. The CPU is utilized to dispatch the simulation and perform serial computing. Compared with the conventional simulation tool, the simulation speed of the 3‐D wind inflow model is highly improved, which fulfils the requirement of the real‐time wind field simulation. The hardware architecture of the framework is designed to be highly extensible by multiple computing nodes for 3‐D wind inflow, wake dynamic, and wind turbine model. The extendability enables the ability for large‐scale wind field simulation with high efficiency. A 5 km$\rm km$ × 2 km$\rm km$ × 0.35 km$\rm km$ wind field consisting of three wind turbines is used as the case. The case study was conducted and analyzed, proving that the framework can capture the detailed wake dynamic, wind turbine dynamic, and wind inflow dynamic. Meanwhile, the calculation speed of disturbed wind speed increased by 264 times. [ABSTRACT FROM AUTHOR]

NAS Parallel Benchmarks (NPB) is a standard benchmark suite used in the evaluation of parallel hardware and software. Several research efforts from academia have made these benchmarks available with different parallel programming models beyond the original versions with OpenMP and MPI. This work joins these research efforts by providing a new CUDA implementation for NPB. Our contribution covers different aspects beyond the implementation. First, we define design principles based on the best programming practices for GPUs and apply them to each benchmark using CUDA. Second, we provide ease of use parametrization support for configuring the number of threads per block in our version. Third, we conduct a broad study on the impact of the number of threads per block in the benchmarks. Fourth, we propose and evaluate five strategies for helping to find a better number of threads per block configuration. The results have revealed relevant performance improvement solely by changing the number of threads per block, showing performance improvements from 8% up to 717% among the benchmarks. Fifth, we conduct a comparative analysis with the literature, evaluating performance, memory consumption, code refactoring required, and parallelism implementations. The performance results have shown up to 267% improvements over the best benchmarks versions available. We also observe the best and worst design choices, concerning code size and the performance trade‐off. Lastly, we highlight the challenges of implementing parallel CFD applications for GPUs and how the computations impact the GPU's behavior. [ABSTRACT FROM AUTHOR]

In recent years, mobile laser scanning (MLS) has attracted increasing interest for road network three-dimensional mapping, where one of the applications of MLS data is automation in urban road manhole covers detection and their information measurement for monitoring and management of manhole covers on regular-basis. Therefore, a multi-step method is proposed based on geometric and radiometric constraints on manhole covers for their extraction and maintenance-related information measurement. The proposed method was implemented using graphics processing unit (GPU)- based parallel computing framework with improved computation time. The method performance was evaluated using MLS datasets of two complex urban roadway test sites, which included partially overlapping objects, occluded road surfaces, and intra-class variability. The manhole covers were extracted at average completeness, correctness and quality of 96.69%, 98.32%, and 95.12%, respectively. The proposed method performed satisfactorily in the challenging cases of road manhole covers and achieves significant improvement in comparison with several state-of-the-art methods. [ABSTRACT FROM AUTHOR]

The development of parallel applications is a difficult and error-prone task, especially for inexperienced programmers. Stencil operations are exceptionally complex for parallelization as synchronization and communication between the individual processes and threads are necessary. It gets even more difficult to efficiently distribute the computations and efficiently implement communication when heterogeneous computing environments are used. For using multiple nodes, each having multiple cores and accelerators such as GPUs, skills in combining frameworks such as MPI, OpenMP, and CUDA are required. The complexity of parallelizing the stencil operation increases the need for abstracting from the platform-specific details and simplify parallel programming. One way to abstract from details of parallel programming is to use algorithmic skeletons. This work introduces an implementation of the MapStencil skeleton that is able to generate parallel code for distributed memory environments, using multiple nodes with multicore CPUs and GPUs. Examples of practical applications of the MapStencil skeleton are the Jacobi Solver or the Canny Edge Detector. The main contribution of this paper is a discussion of the difficulties when implementing a universal Skeleton for MapStencil for heterogeneous computing environments and an outline of the identified best practices for communication intense skeletons. [ABSTRACT FROM AUTHOR]

The CUDA core of NVIDIA GPUs had been one of the most efficient computation units for parallel computing. However, recent rapid developments in deep neural networks demand an even higher level of computational performance. To meet this requirement, NVIDIA has introduced the Tensor core in recent generations. However, their impressive enhancements in computational performance have newly brought high pressure on the memory hierarchy. In this paper, first we identify the required memory bandwidth in the memory hierarchy as the computational performance increases in actual GPU hardware. Through a comparison of the CUDA core and the Tensor core in V100, we find that the tremendous performance increase of the Tensor core requires much higher memory bandwidth than that in the CUDA core. Moreover, we thoroughly investigate memory bandwidth requirement over Tensor core generations of V100, RTX TITAN, and A100. Lastly, we analyze a hypothetical next-generation Tensor core introduced by NVIDIA through a GPU simulation, through which we propose an inter-warp multicasting microarchitecture that reduces redundant shared memory (SMEM) traffic during the GEMM process. Our evaluation shows that inter-warp multicasting reduces the SMEM bandwidth pressure by 33% and improves the performance by 19% on average in all layers of ResNet-152 and BERT-Large. [ABSTRACT FROM AUTHOR]

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In this paper, a time-explicit Finite-Volume method is adopted to solve the 2-D shallow water equations on an unstructured triangular mesh, using a two-stage Runge-Kutta integrator and a monotone MUSCL model to achieve second-order accuracy in time and space, respectively. A multi-GPU model is presented that uses the Message Passing Interface (MPI) with OpenACC and uses the METIS library to produce the domain decomposition. A CUDA-aware MPI library (GPUDirect) and overlapped MPI communication with computation are used to improve parallel performance. Two benchmark tests with wet and dry downstream beds are used to test the code's accuracy. Good results were achieved compared to the numerical simulations of published studies. Compared with the multi-CPU version of a 6-core CPU, maximum speedups of 56.18 and 331.51 were obtained using a single GPU and 8 GPUs, respectively. Higher mesh resolution enhances acceleration performance, and the model is applicable to other environmental modeling activities. • We expressed the shallow-water equations for a 2D area for numerical solution via parallel computation using MPI and OpenACC. • Various parallel computing techniques are optimized to improve the code's performance. • The single-GPU version obtained a speedup factor of 56.18 compared to the 6-core multi-CPU version. • A speedup of 331.51 was achieved by the multi-GPU version over the 6-core workstation processor version. [ABSTRACT FROM AUTHOR]

In this paper we present a scalable approach based on the latency-based linear multistep compound method to use graphic processing unit (GPU) to accelerate the power system simulations with electromagnetic transients. To balance between the computational load and accuracy, we modeled the power system using shifted frequency analysis. Then, to efficiently exploit the hardware, our computational approach is designed to utilize both data-parallel and task-parallel execution. In addition, a graph-based thread safety design is introduced to achieve high scalability in the paralleled component computations. Furthermore, our implementation introduces a translation layer for different heterogeneous computing frameworks during compile time, so that a wide range of GPU devices can be supported without losing performance. Finally, benchmark results show that our approach achieves faster-than-real-time capability for systems with hundreds to thousands of nodes. [Display omitted] • Exploits data- and task-parallelism together in an automated way. • A graph-based approach to ensure thread safety to increase scalability. • A compile-time translation layer to allow execution on various platforms. • Faster-than-real-time for system with more than 10,000 dynamic components. • 82 × faster compared to an optimized sequential simulation. [ABSTRACT FROM AUTHOR]

Existing image databases contain a few diversity of images. Likewise, there is no specific image base available in other situations, leading to the need to undertake additional efforts in capturing images and creating datasets. Many of these datasets contain only a single object in each image, but often the scenario in which projects must operate in production requires several objects per image. Thus, it is necessary to expand original datasets into more complex ones with specific combinations to achieve the goal of the application. This work proposes a technique for image generation to extend an initial dataset. It has been designed generically to work with various images and create a data set from some initial images. The generated set of images is used in a distributed environment. It is possible to perform image generation in this environment, producing datasets with specific images to work in certain applications. The generation of images consists of two methods: generation by deformation and generation by a neural network. With the proposed methods, this work sought to bring as main contributions the specification and implementation of an image generating component so that it is possible to easily integrate it with possible heterogeneous devices capable of parallel computing, such as General Purpose Graphics Processing Unit (GPGPU). In comparison with the existing methods to the proposed one, this one proposes to use the image generator enlarging an initial image bank with the combination of two methods. Some experiments are presented doing generation with handwritten digits to validate the proposed approach. The generator was designed with CUDA and GPU-optimized libraries as TensorFlow-specific modules. The results obtained can optimize the integration process with the simulation of possible stimuli choices, avoiding problems in the generation of image phase tests. [ABSTRACT FROM AUTHOR]

As an improved method of lattice Boltzmann method (LBM), regularized lattice Boltzmann method (RLBM) has been applied to simulate fluid flow. Nevertheless, the performance of RLBM needs to be considered when simulating actual problems. The rise of multicore platforms, especially the popularity of graphics processor units (GPUs), has provided possible implementation solutions for parallel computing. In this article, an RLBM parallel model on the CPU/GPU heterogeneous platforms is proposed. To solve the problem of possible GPU memory shortage, the CPU controls the startup of the kernel function in the RLBM algorithm and participates in the calculation. Due to the characteristics of the algorithm, the entire flow field is divided into CPU computing areas and GPU computing areas according to the given flow field division rules. OpenMP and CUDA are, respectively, applied to CPU and GPU for parallel computing. The startup of the kernel function takes a short time, and the CPU and GPU can be approximately regarded as performing calculations simultaneously. Since the data exchange between the CPU and GPU has a significant impact on performance, a buffer is set at the boundary of the CPU and GPU to reduce the frequency of data exchange. The buffer size determines the number of program iterations before exchanging data. The performance of the algorithm is measured by MFLUPS, and the algorithm is applied to the 3D lid‐driven cavity flow. The obtained results show that the MFLUPS of the algorithm is 25 times that of CPU MFLUPS, and it adds an increment equivalent to CPU MFLUPS compared with GPU MFLUPS. And the algorithm is extended to a multi‐GPU version, which is also applied to the 3D lid‐driven cavity flow. The results obtained show that the MFLUPS of the multi‐GPU version is 1.8 times that of the single GPU. [ABSTRACT FROM AUTHOR]

In this work, we consider the problem of calculating the generalized Moore–Penrose inverse, which is essential in many applications of graph theory. We propose an algorithm for the massively parallel systems based on the recursive algorithm for the generalized Moore–Penrose inverse, the generalized Cholesky factorization, and Strassen's matrix inversion algorithm. Computational experiments with our new algorithm based on a parallel computing architecture known as the Compute Unified Device Architecture (CUDA) on a graphic processing unit (GPU) show the significant advantages of using GPU for large matrices (with millions of elements) in comparison with the CPU implementation from the OpenCV library (Intel, Santa Clara, CA, USA). [ABSTRACT FROM AUTHOR]

Correlation for radio interferometer array applications, including Very Long Baseline Interferometry (VLBI), is a multidisciplinary field that traditionally involves astronomy, geodesy, signal processing, and electronic design. In recent years, however, high-performance computing has been taking over electronic design, complicating this mix with the addition of network engineering, parallel programming, and resource scheduling, among others. High-performance applications go a step further by using specialized hardware like Graphics Processing Units (GPUs) or Field Programmable Gate Arrays (FPGAs), challenging engineers to build and maintain high-performance correlators that efficiently use the available resources. Existing literature has generally benchmarked correlators through narrow comparisons on specific scenarios, and the lack of a formal performance characterization prevents a systematic comparison. This combination of ongoing increasing complexity in software correlation together with the lack of performance models in the literature motivates the development of a performance model that allows us not only to characterize existing correlators and predict their performance in different scenarios but, more importantly, to provide an understanding of the trade-offs inherent to the decisions associated with their design. In this paper, we present a model that achieves both objectives. We validate this model against benchmarking results in the literature, and provide an example for its application for improving cost-effectiveness in the usage of cloud resources. [ABSTRACT FROM AUTHOR]

Nowadays, with the rapid growth of data volume, massive data has become one of the factors that plague the development of enterprises. How to effectively process data and reduce the concurrency pressure of data access has become the driving force for the continuous development of big data solutions. This article mainly studies the MapReduce parallel computing framework based on multiple data fusion sensors and GPU clusters. This experimental environment uses a Hadoop fully distributed cluster environment, and the entire programming of the single-source shortest path algorithm based on MapReduce is implemented in Java language. 8 ordinary physical machines are used to build a fully distributed cluster, and the configuration environment of each node is basically the same. The MapReduce framework divides the request job into several mapping tasks and assigns them to different computing nodes. After the mapping process, a certain intermediate file that is consistent with the final file format is generated. At this time, the system will generate several reduction tasks and distribute these files to different cluster nodes for execution. This experiment will verify the changes in the running time of the PSON algorithm when the size of the test data set gradually increases while keeping the hardware level and software configuration of the Hadoop platform unchanged. When the number of computing nodes increases from 2 to 4, the running time is significantly reduced. When the number of computing nodes continues to increase, the reduction in running time will become less and less significant. The results show that NESTOR can complete the basic workflow of MapReduce, and simplifies the process of user development of GPU positive tree order, which has a significant speedup for applications with large amounts of calculations. [ABSTRACT FROM AUTHOR]

In this article, an efficient approach based on the parallel alternating direction implicit (ADI) method is presented for the transient thermal simulation of liquid-cooled 3-D integrated circuits (ICs). To accurately characterize the thermal behaviors, a compact thermal model based on finite-difference approximation is established. The ADI method with linear time complexity is utilized to reduce computational cost, which can easily deal with large-scale problems. To suppress the oscillations of transient results in the case of large time steps, an effective technique using the exponentially expanding subtime steps is introduced, which improves the accuracy of results significantly. In addition, taking the advantage of parallel computing, the transient simulation is further accelerated by the parallel cyclic reduction (PCR) algorithm implemented on graphics processing units (GPUs). The accuracy and efficiency of the proposed method are demonstrated by several numerical examples. [ABSTRACT FROM AUTHOR]

In the past decade, high performance compute capabilities exhibited by heterogeneous GPGPU platforms have led to the popularity of data parallel programming languages such as CUDA and OpenCL. Developing high performance parallel programming solutions using such languages involve a steep learning curve due to the complexity of the underlying heterogeneous compute devices and their impact on performance. This has led to the emergence of several High Performance Computing frameworks which provide high-level abstractions for easing the development of data-parallel applications on heterogeneous platforms. However, the scheduling decisions undertaken by such frameworks only exploit coarse-grained concurrency in data parallel applications. In this paper, we propose PySchedCL, a framework which explores fine-grained concurrency aware scheduling decisions that harness the power of heterogeneous CPU/GPU architectures efficiently. We showcase the efficacy of such scheduling mechanisms over existing coarse-grained dynamic scheduling schemes by conducting extensive experimental evaluations for a diverse set of popular Deep Learning benchmarks. [ABSTRACT FROM AUTHOR]

We present Heterogeneous Parallel Virtual Machine (HPVM), a compiler framework for hardware-agnostic programming on heterogeneous compute platforms. HPVM introduces a hardware-agnostic parallel intermediate representation with constructs for the hierarchical task, data, and pipeline parallelism, including dataflow parallelism, and supports multiple front-end languages. In addition, HPVM provides optimization passes that navigate performance, energy, and accuracy tradeoffs, and includes retargetable back ends for a wide range of diverse hardware targets, including central processing units, graphics processing units, domain-specific accelerators, and field-programmable gate arrays. Across diverse hardware platforms, HPVM optimizations provide significant performance and energy improvements, while preserving object-code portability. With these capabilities, HPVM facilitates developers, domain experts, and hardware vendors in programming modern heterogeneous systems. [ABSTRACT FROM AUTHOR]

Many studies have focused on the acceleration of computational fluid dynamics (CFD) using multicore hardware such as graphics-processing units (GPUs) in the field of parallel computing. In GPU acceleration, CFD parallel granularity generally refers to the point granularity parallelization as a unit of the grid. An implicit time advancement scheme is more efficient and faster than an explicit time advancement scheme for CFD. However, for commonly used implicit schemes, such as the lower-upper symmetric Gauss–Seidel (LUSGS) scheme, the parallel dimensionality is reduced, resulting in a highly time-consuming procedure. In this paper, the data-parallel upper-lower relaxation (DPLUR) scheme based on Jacobi iteration is used and then implemented on a GPU. Numerical experiments are carried out and show that the computing speed of point granularity parallelization using the DPLUR scheme, especially implemented on a GPU, is much higher than that of dimensionality reduction using the LUSGS scheme. Moreover, the influence of different Jacobi inner iteration steps (JIIS) on the convergence time is discussed, and two JIIS optimization algorithms are proposed according to the characteristics of convergence. On the basis of the memory access form, a DPLUR red–black (DPRB) scheme with more stable and faster convergence than the conventional DPLUR scheme is developed. Finally, some standard cases are adopted to verify the effectiveness of DPRB schemes with the JIIS optimization algorithm. [ABSTRACT FROM AUTHOR]

Advanced network services, such as firewalls, policy-based routing, and virtual private networks, must rely on routers to classify packets into different flows based on packet headers and predefined filter tables. When multiple filters are overlapped, conflicts may occur, leading to ambiguity in the packet classification. Conflict detection ensures the correctness of packet classification and has received considerable attention in recent years. However, most conflict-detection algorithms are implemented on a conventional central processing unit (CPU). Compared with a CPU, a graphics processing unit (GPU) exhibits higher computing power with parallel computing, hence accelerates the execution speed of conflict detection. In this study, we employed a GPU to develop two efficient algorithms for parallel conflict detection: the general parallel conflict-detection algorithm (the GPCDA) and the enhanced parallel conflict-detection algorithm (the EPCDA). In the GPCDA, we demonstrate how to perform conflict detection through parallel execution on GPU cores. While in the EPCDA, we analyze the critical procedure in conflict detection as to reduce the number of matches required for each filter. In addition, the EPCDA adopts a workload balance method to enable load balancing of GPU execution threads, thereby significantly improving performance. The simulation results show that with the 100 K filter database, the GPCDA and the EPCDA execute conflict detection 2.8 to 13.9 and 9.4 to 33.7 times faster, respectively, than the CPU-based algorithm. [ABSTRACT FROM AUTHOR]

In computed tomography (CT), the total variation (TV) constrained algebraic reconstruction technique (ART) can obtain better reconstruction quality when the projection data are sparse and noisy. However, the ART-TV algorithm remains time-consuming since it requires large numbers of iterations, especially for the reconstruction of high-resolution images. In this work, we propose a fast algorithm to calculate the system matrix for line intersection model and apply this algorithm to perform the forward-projection and back-projection operations of the ART. Then, we utilize the parallel computing techniques of multithreading and graphics processing units (GPU) to accelerate the ART iteration and the TV minimization, respectively. Numerical experiments show that our proposed parallel implementation approach is very efficient and accurate. For the reconstruction of a 2048 × 2048 image from 180 projection views of 2048 detector bins, it takes about 2.2 seconds to perform one iteration of the ART-TV algorithm using our proposed approach on a ten-core platform. Experimental results demonstrate that our new approach achieves a speedup of 23 times over the conventional single-threaded CPU implementation that using the Siddon algorithm. [ABSTRACT FROM AUTHOR]

Real-time three-dimensional (3D) reconstruction has been widely explored in several domains in motion capture, robot navigation, augmented reality, and autonomous driving. It is considered one of the most efficient solutions to overcome several problems, such as occlusion and collision in computer vision and computer graphics. This process is computationally intensive and it considers a bottleneck for real-time realistic interaction applications which need a quick response to achieve action in real-time. The Monocular 3D model reconstruction (M3DMR) is considered one of the possible solutions to build an accurate 3D reconstruction in a dynamic environment. However, the proposed framework needs a high computational power to create a single frame. Graphics processors unit (GPU) architecture is used to improve the computational time of M3DMR. This study discussed how to maximize the benefits of using GPU resources by using several optimization techniques that enable GPU architecture to achieve the best possible performance for the M3DMR. Different multicore heterogeneous systems are used to evaluate the performance of the proposed framework. Experimental results confirm that our parallel implementation of 3D Model Reconstruction of Monocular Video Frames is valid for different GPU architectures. The proposed parallel implementation can execute 28 FBS compared with the serial version that executes one frame in 30 min. [ABSTRACT FROM AUTHOR]