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Formal methods have been introduced as the efficient approach for Trojan detection using the model checking approach. However, systematic property generation for detecting a wide range of Trojans is the main challenge in these methods. In other words, the efficient property generation to pinpoint projected Trojan precisely in targeted hardware has been a bottleneck in this approach. This paper evaluated the feasibility of the systematic property generation methodology for Trojan detection in Cryptosystems by analyzing the vulnerable points of an implemented design respecting Trojans' covered class. The vulnerability analysis reduces the search space of formal methods and considerably improves the scalability of these methods. We have shown in this research that these properties can be generated systematically and prove that the generated properties can be used in conventional model-checking tools to find hard-to-detect Trojans efficiently. Experimental results show that the proposed method reduces Trojan detection time considerably. Also, the memory required to evaluate circuits is possible for several hundreds of clock cycles. [ABSTRACT FROM AUTHOR]

Outsourcing of the design and IC fabrication to the untrusted entities increases the risk of hardware Trojan insertion in different stages of IC’s life cycle. In this brief, we propose a pre-silicon modification scheme, aiming at detecting and compensating the adverse effect of timing hardware Trojans (THT) using a time borrowing approach. The key idea is that a circuit path under tamper in which the setup time is violated can borrow some time from the following stage if it has enough positive timing slack to donate. Accordingly, we modify the original circuit by employing the Dynamic flip-flop Conversion (DFFC) structures to convert the suspected flip-flops into a single transparent latch. A new timing vulnerability analysis including the path-delay and structural analysis along with the proposed test pattern generation scheme is also developed to exploit the vulnerable paths suitable for DFFC insertion. The experimental results show that the insertion of DFFC structures can effectively predict timing errors higher than 1.4% of the critical path-delay while it can fully restore the Trojan-infected paths back to its normal state by compensating 100% of the injected delays ranging from 39% to 81% of the critical path. [ABSTRACT FROM AUTHOR]

With the rapid growth in IC outsourcing in the semiconductors industry, concerns have increased about the weakening ICs security against hardware Trojan attacks. In this brief, an integrated hardware Trojan detection and localization methodology is presented by employing the proposed SAT-based test pattern generation scheme and the MUX-based debugging technique. The experimental results show that our methodology can effectively detect timing anomalies in the path-delays caused by hardware Trojans with node coverage around 97% as well as localizing all Trojan’s gates with a localization resolution around 99.6%. Moreover, all timing error sites are successfully identified with zero False Negative and 0.56% False Positive rates. [ABSTRACT FROM AUTHOR]

Hardware Trojan attacks have emerged as a major security issue for hardware at different level of abstractions, which relate to malicious tampering of a hardware during design or fabrication process. In this paper, a new low overhead and high speed design for trust methodology for increasing both full activation and side channel sensitivity of Trojan is proposed. The main idea is that the increase in transition probability of individual nets does not necessarily increase the transition probability of the succeeding nets of the circuit. Accordingly, the rules and conflicts of the propagation of maximum transition probability for individual gates have been presented to ensure that a full transition path is constructed between each low transition probability net and primary inputs of the circuit. The results show that the proposed methodology achieves superior efficiency in Trojan full activation by more than $4 \times $ through logic testing approach besides higher sensitivity averagely around $20 {\times }$ for power-based side channel analysis compared to existing methods. [ABSTRACT FROM AUTHOR]

In range analysis (RA), suitable integer bit-widths are assigned to the variables so that no overflow occurs. Although the accuracy in RA rather than error analysis has more impact on hardware cost and efficiency, there are few works that offer new approaches to improve RA. Arithmetic functions, mostly represented by polynomials, are normally suitable for both optimization and verification purposes. In this paper, a safe and more accurate RA of feed-forward fixed-point polynomial data-flow graphs is proposed. The method employs particular features of RA and maps it to a specific class of polynomial optimization problems. The proposed method provides tighter ranges while taking less runtime in comparison with satisfiability-modulo theory-based method. Furthermore, the improved ranges lead to enhance the area and delay efficiency more than 50% and 24%, respectively, when the circuits are implementing the functions in comparison with the state-of-the-art techniques. [ABSTRACT FROM PUBLISHER]

In this brief, we introduce an architecture for accelerating convolution stages in convolutional neural networks (CNNs) implemented in embedded vision systems. The purpose of the architecture is to exploit the inherent parallelism in CNNs to reduce the required bandwidth, resource usage, and power consumption of highly computationally complex convolution operations as required by real-time embedded applications. We also implement the proposed architecture using fixed-point arithmetic on a ZC706 evaluation board that features a Xilinx Zynq-7000 system on-chip, where the embedded ARM processor with high clocking speed is used as the main controller to increase the flexibility and speed. The proposed architecture runs under a frequency of 150 MHz, which leads to 19.2 Giga multiply accumulation operations per second while consuming less than 10 W in power. This is done using only 391 DSP48 modules, which shows significant utilization improvement compared to the state-of-the-art architectures. [ABSTRACT FROM AUTHOR]

By increasing the complexity of digital systems, verification and debugging of such systems have become a major problem and economic issue. Although many computer aided design (CAD) solutions have been suggested to enhance efficiency of existing debugging approaches, they are still suffering from lack of providing a small set of potential error locations and also automatic correction mechanisms. On the other hand, the ever-growing usage of digital signal processing (DSP), computer graphics and embedded systems applications that can be modeled as polynomial computations in their datapath designs, necessitate an effective method to deal with their verification, debugging and correction. In this paper, we introduce a formal debugging approach based on static slicing and dynamic ranking methods to derive a reduced ordered set of potential error locations. In addition, to speed up finding true errors in the presence of multiple design errors, error candidates are sorted in decreasing order of their probability of being an error. After that, a mutation-based technique is employed to automatically correct bugs even in the case of multiple bugs. In order to evaluate the effectiveness of our approach, we have applied it to several industrial designs. The experimental results show that the proposed technique enables us to locate and correct even multiple bugs with high confidence in a short run time even for complex designs of up to several thousand lines of RTL code. [ABSTRACT FROM PUBLISHER]