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The comparator can be described as one of the basic building blocks in electronics. It is implemented both as a discrete device and as a constituent of a complex circuit. In both cases, the circuits usually operate in conditions, where useful and unwanted (noise) signals are present at the same time. In order to maintain the validity of output data, a hysteresis parameter is introduced to the comparator’s circuit. This article presents the results of a CMOS comparator with hysteresis design – the schematic, topology and simulation results are analyzed. The designed comparator is implemented in a zero voltage offset compensation circuit ADC in a multi-standard transceiver IC. Article in Lithuanian. 65 nm KMOP technologijos histerezinio komparatoriaus projektavimas Santrauka Komparatorius yra vienas iš pagrindinių elektronikos įtaisų. Jis yra naudojamas kaip diskretinis elementas arba kaip viena iš sudėtingesnės sistemos sudedamųjų dalių. Šie įtaisai dažnai veikia elektronikos sistemose, kuriose egzistuoja ne tik informaciją nešantys bei apdorojami signalai, bet ir nepageidautini triukšmo signalai. Siekiant tokiomis sąlygomis užtikrinti patikimą ir efektyvią komparatoriaus veiką, imama taikyti histerezė. Šiame straipsnyje pateikiami TSMC 65 nm KMOP histerezinio komparatoriaus projektavimo rezultatai: aptariama principinė elektrinė schema, pateikiama suprojektuota topologija, jos kompiuterinio modeliavimo rezultatai bei išvados. Šis komparatorius bus naudojamas daugiastandarčio, daugiakanalio siųstuvo-imtuvo grandinėje, nulinio potencialo poslinkio įtampą nustatančiame, lygiagrečios architektūros analoginiame skaitmeniniame keitiklyje (ASK). Reikšminiai žodžiai:KMOP, komparatorius, histerezė, integrinis grandynas, lustas, analoginis skaitmeninis keitiklis.

In this paper, design and simulation results of an 8-bit 1 GS/s clock speed folding and interpolating analog-digital converter (F&I ADC) are presented. The converter for four lower bits used folding with interpolation whose coefficients respectively equal to 8 and 6, and four upper bits made using parallel comparators structure. ADC design and simulations carried out with Cadence software packages. Dynamic characteristics of the converter are presented, which shows that signal-to-noise and distortion ratio (SNDR) and spurious-free dynamic range (SFDR) at 1 MHz input signal and 1 GS/s clock frequency is respectively equal to 49,7/54,6 dB. It is also identified effective number of bits (ENOB), which is approximately equal to 8-bit, when the input signal frequency is 1 MHz and at 500 MHz, ENOB drops to around 6-bit. After static characteristics simulation were got that the differential nonlinearity (DNL) did not exceed ±0,4 LSB and integral nonlinearity (INL) is less than ±0,6 LSB.

We have been simulated the submicron CMOS charge sensitive preamplifier (CSP) with the leakage current compensation circuit, which allows reducing equivalent noise charge up to 54 electrons. Simulation has been performed with SPICE simulators using the BSIMV3.3 transistors parameters of the MOSIS 0.13 µm CMOS. The value of the feedback capacitor Cfb is chosen as the CGD≈1 fF capacitance of input transistors. The feedback resistance Rfb is implemented by PMOS transistors operating in the linear region. CSP has the following main electrical parameters: the minimum of ENC is in the leakage current region -3 nA…+6 nA and equal 54…70 ē, total gain of the chain is K=41.42 mV/kē, while the peaking time is τp≈35 ns. It is a promising solution for X-ray pixel detectors.