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Network-on-chip facilitates glueless interconnection of various on-chip components in the forthcoming system-on-chips. As in the case of any new technology, security is a major concern in network-on-chip (NoC) design too. In this work, we explore a covert threat model for multiprocessor system-on-chips (MPSoCs) stemming from the use of malicious third-party network-on-chips (NoCs). We illustrate that a rogue NoC (rNoC) can selectively disrupt the perceived availability of on-chip resources, thereby causing large performance bottlenecks for the applications running on the MPSoC platform. Further, to counter the threat posed by rNoC, we propose a runtime latency auditor that enables an MPSoC integrator to monitor the trustworthiness of the deployed NoC throughout the chip lifetime. We also discuss measures that can be taken to minimize the impact of a rNoC, once it is detected. Our comprehensive cross-layer analysis of our novel detection technique indicates modest overheads of 12.73% in area, 9.844% in power, and 5.4% in terms of network latency.

Continuous technology scaling has made aging mechanisms, such as negative bias temperature instability and electromigration primary concerns in network-on-chip (NoC) designs. In this paper, we extensively analyze the effects of these aging mechanisms on NoC routers and links. We observe a critical need of a robust aging-aware routing algorithm that not only reduces power-performance overheads caused due to aging degradation, but also minimizes the stress experienced by heavily utilized routers and links. To solve this problem, we propose an aging-aware adaptive routing algorithm and a router microarchitecture that routes the packets along the paths, which are both least congested and experience minimum aging degradation. After an extensive experimental analysis using real workloads, we observe 13% and 12.17% average overhead reduction in network latency and energy–delay product per flit, a 10.4% improvement in performance, and a 60% improvement in mean time to failure using our aging-aware routing algorithm.

Aggressive technology scaling exacerbates the problem of voltage emergencies in emerging MPSoC systems. Network-on-Chips, the de-facto standard for connecting on-chip components in forthcoming devices play a central role in providing robust and reliable communication. In this work, we propose DrNoC (droop resilient network-on-chip)-two microarchitectural techniques to mitigate voltage emergency-induced timing errors in NoCs and preserve error-free communication throughout the network. DrNoC employs frequency downscaling and a pipeline error-recovery mechanism to reclaim corrupted flits in the router. Compared to the recently proposed NSFTR fault-tolerant technique, DrNoC offers a 27% improvement in energy-delay efficiency.

In this paper, we uncover a novel and imminent threat to an emerging computing paradigm: MPSoCs built with 3rd party IP NoCs. We demonstrate that a compromised NoC (C-NoC) can enable a range of security attacks with an accomplice software component. To counteract these threats, we propose Fort-NoCs, a series of techniques that work together to provide protection from a C-NoC in an MPSoC. Fort-NoCs's foolproof protection disables covert backdoor activation, and reduces the chance of a successful side-channel attack by "clouding" the information obtained by an attacker. Compared to recently proposed techniques, Fort-NoCs offers a substantially better protection with lower overheads. Copyright 2014 ACM.

The trend towards massive parallel computing has necessitated the need for an On-Chip communication framework that can scale well with the increasing number of cores. At the same time, technology scaling has made transistors susceptible to a multitude of reliability issues (NBTI, HCI, TDDB). In this work, we propose an HCI-Tolerant microarchitecture for an NoC Router by manipulating the switching activity around the circuit. We find that most of the switching activity (the primary cause of HCI degradation) are only concentrated in a few parts of the circuit, severely degrading some portions more than others. Our techniques increase the lifetime of an NoC router by balancing this switching activity. Compared to an NoC without any reliability techniques, our best schemes improve the switching activity distribution, clock cycle degradation, system performance and energy delay product per flit by 19%, 26%, 11% and 17%, respectively, on an average.

We present low power correlator circuits for direct sequence spread spectrum receivers. We evaluated the effectiveness of three types of logic families (Static CMOS, CP, Domino) in correlator design. The correlator is simple in its implementation using only summer and delay elements. The circuits were implemented using standard threshold voltage transistors in 90nm CMOS and operated with 0.6V supply. Conclusions regarding power, delay and area trade-offs are made. Baseline circuits were the static CMOS. Simulation results show that a Domino logic implementation results in a least power consumption and delay for a modest trade-off in area, however this comes at the price of complexity. The CPL implementation results in a 30% decrease in area for the same power consumption with a three times increase in delay. The optimum correlator is a domino logic-based correlator that consumes 1.54uW of power with a delay of 1.845ns.