Search

Two grounded voltage controlled resistors operating in saturation region are proposed. The first proposed grounded voltage controlled resistor employs 8 metal-oxide semiconductor (MOS) transistors and the second one uses 10 MOS transistors. The proposed GVCRs having only one control voltage do not need any bias currents and voltages constructed with extra elements. One of the main properties of the proposed tunable resistors is to operate at higher frequencies. The first proposed tunable resistor needs a matching condition between power supply voltages while the second does not require such a matching constraint. A video filter example for the proposed tunable resistors is also given. A number of simulations with SPICE simulation program are included in order to exhibit effectiveness, performance and workability of the proposed tunable resistors. Keywords: Tunable resistor, MOS, Video filter, Voltage controlled © 2014, National Institute of Science Communication and Information Resources (NISCAIR). All rights reserved.

It is well known that there is an increasing trend on the design of low-voltage low-power circuits due to the requirement of efficient portable electronic systems with long battery lifetime. For analog circuits, higher biasing current is needed to obtain the same performance with low supply voltages which, however, results in increasing the power consumption. On the other hand, lower biasing current restricts the dynamic range of the circuit, whereas with low supply voltages it is hard to keep all the transistors in saturation region. Thus, design techniques for low-voltage low-power operation are very important for analog circuit designers. In this Special Issue we deal with low-voltage low-power analog devices and their applications

In this work, we present new topologies for realizing one lossless grounded inductor and two floating, one lossless and one lossy, inductors employing a single differential difference current conveyor (DDCC) and a minimum number of passive components, two resistors, and one grounded capacitor. The floating inductors are based on ordinary dual-output differential difference current conveyor (DO-DDCC) while the grounded lossless inductor is based one a modified dual-output differential difference current conveyor (MDO-DDCC). The proposed lossless floating inductor is obtained from the lossy one by employing a negative impedance converter (NIC). The non-ideality effects of the active element on the simulated inductors are investigated. To demonstrate the performance of the proposed grounded inductance simulator as an example, it is used to construct a parallel resonant circuit. SPICE simulation results are given to confirm the theoretical analysis.

In this paper, a new fully CMOS four-quadrant multiplier based on plus-type second-generation current conveyors (CCII+s) is presented. The proposed circuit employs only two CCII+s and two NMOS transistors as active devices, without the need for any external passive elements. Functionality of the new circuit is demonstrated through SPICE simulations performed using 0.25 mu m CMOS process technology parameters. In addition, simulation results of an amplitude modulator realized with the proposed multiplier are included.

In this paper, three squarer configurations and a current-mode (CM) full-wave rectifier circuit are suggested. The first and second squarer configurations respectively use two PMOS and two NMOS transistors while the third one employs three PMOS and one NMOS transistors. A CM full-wave rectifier with high output impedance current is developed. All of the proposed circuits provide several advantages such as low number of components and less power consumption. The proposed circuits are simulated using SPICE program to demonstrate their performance and workability.

In this paper a new CMOS realization for third generation current conveyor (CCIII) is proposed. The proposed circuit provides high swing range at terminals X and Y. The circuit has low input impedances at terminals X and Y and high output impedance at terminals Z+ and Z-. The circuit has 180MHz -3dB cutoff frequency in voltage follower mode. SPICE simulation results using MIETEC 1.2 CMOS process model are given.

In this paper two new current-mode multifunction filters are presented. The proposed circuits are composed of two internally compensated operational amplifiers (OAs) and three dual-output operational transconductance amplifiers (OTAs), without using external passive elements. Each proposed multifunction filter can realize band-pass, bandstop, and lowpass or highpass responses simultaneously all at high output impedances. No matching conditions are required. The circuits are suitable for monolithic implementation either with CMOS or bipolar technologies. All of active sensitivities are low. The performances of the circuits are confirmed through a SPICE simulation program using the model parameters of 0.5 mum MIETEC CMOS technology.

In this paper, three squarer configurations and a current-mode (CM) full-wave rectifier circuit are suggested. The first and second squarer configurations respectively use two PMOS and two NMOS transistors while the third one employs three PMOS and one NMOS transistors. A CM full-wave rectifier with high output impedance current is developed. All of the proposed circuits provide several advantages such as low number of components and less power consumption. The proposed circuits are simulated using SPICE program to demonstrate their performance and workability.

In this study, a novel synthetic transformer (ST), namely mutually coupled circuit, using commercially available active components such as current feedback operational amplifiers (CFOAs) is proposed. The proposed ST uses four CFOAs, two grounded capacitors and five resistors. It possesses only resistors but no capacitors attached in series to W/X terminals of the CFOAs; consequently, its high-frequency performance is well. Nevertheless, it needs a single matching condition for symmetrical coupling. As an application example, a double-tuned band-pass filter is given. The validity of the proposed circuit is demonstrated through several SPICE simulations and experiments. © 2020, Springer Science+Business Media, LLC, part of Springer Nature.

In this paper, a new current-mode instrumentation amplifier with electronic tuning and low-voltage operation capabilities is presented. Simplicity is other important feature so that the whole circuit is composed of only 20 transistors. All the above have been achieved using MOS transistors biased in the sub-threshold region. The required current-controlled gain stage has been implemented using an appropriate translinear loop which is fed by the output of a current subtraction stage, realized through the employment of flipped voltage follower based current-mirrors. The performance of the presented amplifier is evaluated through simulation results, using the Cadence suite and MOS transistors models provided by the Austria Mikro Systeme 0.35 μ m CMOS process. The differential gain was 20 – 40 dB , the Common-Mode Rejection Ratio (CMRR) was 44.4 – 48.9 dB , achieved at power dissipation 72.75 – 386.1 nW . The bandwidth was 7 kHz and the Total Harmonic Distortion (THD) was 2 % for an input signal with amplitude equal to 550 pA. As an application example, the proposed current-mode instrumentation amplifier has been employed for removing the noise component in electrocardiogram signals.

Minaei, Shahram (Dogus Author) In this paper a new low-voltage low-power instrumentation amplifier (IA) is presented. The proposed IA is based on supply current sensing technique where Op-Amps in traditional IA based on this technique are replaced with voltage buffers (VBs). This modification results in a very simplified circuit, robust performance against mismatches and high frequency performance. To reduce the required supply voltage, a low-voltage resistor-based current mirror is used to transfer the input current to the load. The input and output signals are of voltage kind and the proposed IA shows ideal infinite input impedance and a very low output one. PSPICE simulation results, using 0.18 μm TSMC CMOS technology and supply voltage of ±0.9 V, show a 71 dB CMRR and a 85 MHz constant −3 dB bandwidth for differential-mode gain (ranging from 0 dB to 18 dB). The output impedance of the proposed circuit is 1.7 Ω and its power consumption is 770 µW. The method introduced in this paper can also be applied to traditional circuits based on Op-Amp supply current sensing technique.

Minaei, Shahram (Dogus Author) The authors present two new metal oxide semiconductor field effect transistor (MOSFET)-only second-order voltage and transadmittance-mode band-pass filters (BPFs) employing only five transistors without using any passive elements such as a resistor, a capacitor, and an inductor. As a result, both proposed circuits possess low-power consumption and occupy small chip area. The first proposed filter enjoys low output impedance and offset cancellation for voltage-mode operation while the second proposed filter has low supply voltage. The centre frequency of both proposed filters can be electronically tuned by varying biasing voltage. To demonstrate the performance of the proposed filters, effects of output transconductance of transistors have been investigated and equations of input referred noise have been obtained. Furthermore, fourth-order voltage and transadmittance-mode BPF which is derived the first proposed filter is presented and its simulation results are given. All proposed filters are laid-out in the Cadence environment using Taiwan semiconductor manufacturing company (TSMC) 0.18 μm complementary metal oxide semiconductor (CMOS) technology parameters. The required chip area of the fourth-order voltage and transadmittance-mode band-pass filter is 1100 μm2 and the power consumption is about 436 μW.

Minaei, Shahram (Dogus Author) In this paper, new analog memristor emulator circuits based on current backward transconductance amplifier (CBTA) and passive elements are proposed. They emulate both types of memristor (incremental and decremental) just by interchanging the CBTA output terminals. It uses only one CBTA, two resistors, one capacitor and one multiplier emulating grounded memristor. They consist of less CMOS transistors and have wider output ranges compared to other designed emulator circuits. The CMOS implementation of the CBTA using 0.18 ttm level-7 TSMC CMOS technology parameters is also proposed. It uses 23 CMOS transistors operating with the +/- 0.9 V DC supply voltage. Theoretical derivations and related results are validated using SPICE simulations.

In this study, we present two new grounded capacitance multiplier circuits based on a negative-type second-generation current conveyor (CCII-) and an inverting second-generation current conveyor (ICCII). The first proposed circuit consists of one CCII- and a voltage follower (VF) employing two NMOS transistors while the second proposed circuit is composed of an ICCII and an inverting voltage follower (IVF) including two NMOS transistors. Each circuit contains two resistors, and single grounded capacitor, which is attractive for integrated circuit realization. No active and passive component matching conditions are required for the realization of the proposed capacitance multiplier circuits. The simulation results are included to confirm the theory. (C) 2017 Elsevier GmbH. All rights reserved.

Yıldız, Merih (Dogus Author) -- Minaei, Shahram (Dogus Author) NMOS based circuit realizations of a sinusoidal quadrature oscillator, a transconductance, a transimpedance amplifier are presented. All the circuits are constructed with a voltage-mode “Metamutator” consisting of an analog adder and a subtractor which is one of its possible realizations. The most important feature of the proposed circuits is their extremely simple structures containing only twelve NMOS transistors (six for adder, six for subtractor). Another significant advantage of the proposed circuits is that no external passive element is needed for the oscillator and only one resistor is used for each amplifier circuit; a variable resistor can provide gain adjustability. The post-layout simulations of all the proposed circuits have been executed using TSMC 0.25 µm process parameters with ±1.25 V power supply voltage.

Minaei, Shahram (Dogus Author) A new voltage-mode (VM) proportional integral derivative (PID) controller employing only a single active component named Current Feedback Operational Amplifier (CFOA), two resistors and two grounded capacitors is proposed. The proposed PID controller employs a canonical number of only grounded capacitors without requiring any critical passive component matching conditions and cancellation constraints. It has high input and low output impedances; thus, it can be easily cascaded with other VM structures. It can be easily constructed by a single commercially available active element. Frequency-dependent non-ideal gain and parasitic impedance effects on the performance of the proposed PID controller are investigated. The performance of the proposed PID controller circuit is demonstrated by using PSPICE circuit simulation program and an experiment. Also, 0.18 μm CMOS TSMC technology parameters with ±2 V supply voltages are used. Total power dissipation of the proposed PID controller is 1.64 mW.

In this paper, a new low-power versatile current-mode rectifier is proposed. As a salient feature, the proposed rectifier provides two positive half-wave, two inverting negative half-wave or two full-wave outputs from the same configuration. The proposed circuit employs only a dual-output second-generation current conveyor (DO-CCII) and a core rectifying circuit consisting of twelve MOS transistors. The input and output signals are current. Favorably, by adding two additional transistors, the proposed rectifier can also rectify voltage signals with electronic tuning capability. The simple and MOS only structure of the proposed circuit is highly attractive from integration point of view. In spite of providing multiple outputs at the same time, the proposed rectifier enjoys low power consumption. PSPICE simulations using 0.18 mu m CMOS parameters and supply voltage of +/- 0.9 V demonstrate a precise operation and good temperature stability. (C) 2017 Elsevier GmbH. All rights reserved.

Minaei, Shahram (Dogus Author) In this paper a new topology for implementing Current-Mode Instrumentation Amplifiers (CMIA) is presented. The proposed CMIA is based on two single input-multiple output (SI-MO) current operational amplifiers (COAs) as basic building blocks and 2 resistors. To electronically control the differential mode gain, a transistor operating in triode region is used which acts as a variable resistor. The significant feature of the proposed CMIA is that the active building blocks operate in closed loop configuration. Therefore it exhibits numerous remarkable features such as improved frequency performance, low THD and very low input impedance. In addition, it has fully differential output which reduces the output noise and increases its application. The proposed CMIA is analyzed and simulated with SPICE program using parameters of 0.18 mu m CMOS technology and supply voltage of +/- 0.9 V.

Minaei, Shahram (Dogus Author) The aim of this paper is proposing an alternative method to Gorski-Popiel Technique in realization of synthetic transformers. A new synthetic floating transformer (FT) circuit is also given. The proposed synthetic transformer circuit uses two current backward transconductance amplifiers (CBTAs), three resistors, and two grounded capacitors. The primary selfinductance, the secondary self-inductance, and the mutual inductance can be independently controlled and can be tuned electronically by changing the biasing current of the employed CBTAs. It has a good sensitivity performance with respect to tracking errors. A band-pass filter is also realized to test the performance of the proposed synthetic transformer circuit. The validity of the proposed synthetic transformer circuit is demonstrated by PSPICE simulations and experimental results.

Minaei, Shahram (Dogus Author) -- Yıldız, Merih (Dogus Author) In this paper, a voltage-mode full-wave rectifier circuit is proposed. The proposed full-wave rectifier circuit consists of only a single negative-type second-generation current conveyor, two diodes, and two matched resistors. The proposed circuit, without requiring any external bias voltages and currents, has a simple structure using a minimum number of active and passive components. It is implemented with AMS 0.35 mu m technology operating with +/- 1.65 V. Computer simulation and experimental results are included to verify the theory. (c) 2017 Sharif University of Technology. All rights reserved.

Minaei, Shahram (Dogus Author) In this paper, a new electronically tunable current-mode (CM) first-order universal filter as a new application for inverting second-generation current conveyors (ICCIIs) is proposed. The proposed circuit is based on two ICCII and a capacitor and does not need any resistors and critical passive component matching conditions. It has one input and multiple outputs and simultaneously realizes both inverting and non-inverting first-order low-pass, high-pass and all-pass responses from the same configuration. Employing ICCII as active building block makes possible using a single transistor in linear region as a variable resistor to control filter properties electronically. Nevertheless, the proposed CM first-order universal filter possesses a floating capacitor which can be easily realized in nowadays integrated circuit technologies. It is designed and simulated with SPICE program using 0.13 mu m IBM CMOS parameters and supply voltage of +/- 0.75 V. Non-ideal analysis and Monte Carlo simulation results are also given, which prove good enough response even in the presence of non-idealities and process parameter variations.

A novel topology for realizing voltage-mode (VM) full-wave rectifier/sinusoidal frequency doubler based on current feedback operational amplifiers (CFOAs) and n-channel metal-oxide semiconductor (NMOS) transistors is proposed in this study. The proposed full-wave rectifier structure employs two CFOAs and three enhancement-mode NMOS transistors. With a slight modification, the sinusoidal frequency doubler circuit can be adopted from the full-wave rectifier circuit by replacing a grounded resistor instead of one of the NMOS transistors. Both of the proposed circuits enjoy low output and high input impedance properties which make them convenient for cascading easily with other VM circuits without needing any extra buffer circuits. No passive component matching conditions are needed. The proposed circuits are simulated by using SPICE program to verify the theoretical analysis. © 2017, Springer Science+Business Media, LLC.

Yıldız, Merih (Dogus Author) -- Minaei, Shahram (Dogus Author) In this work, a very compact, rail-to-rail, high-speed buffer amplifier for liquid crystal display (LCD) applications is proposed. Compared to other buffer amplifiers, the proposed circuit has a very simple architecture, occupies a small number of transistors and also has a large driving capacity with very low quiescent current. It is composed of two complementary differential input stages to provide rail-to-rail driving capacity. The push-pull transistors are directly connected to the differential input stage, and the output is taken from an inverter. The proposed buffer circuit is laid out using Mentor Graphics IC Station layout editor using AMS 0.35 mu m process parameters. It is shown by post-layout simulations that the proposed buffer can drive a 1nF capacitive load within a small settling time under a full voltage swing, while drawing only 1.6 mu A quiescent current from a 3.3V power supply.

In this paper, a new voltage-mode (VM) full-wave rectifier circuit employing two plus-type differential voltage–current conveyors, two grounded resistors, and two diodes is proposed. The proposed full-wave rectifier enjoys high input impedance and low output impedance; accordingly, it is suitable for direct cascading with other VM circuits without requiring additional buffers. It employs only two grounded resistors which are advantageous for integrated circuit implementations. However, it needs a single resistor-matching condition. It is simulated using SPICE program to verify the theoretical analysis. © 2016, Springer Science+Business Media New York.

In this paper, the simplest possible electronically adjustable transresistance-mode (TRM) instrumentation amplifier (IA) using only eight MOS transistors is presented. Extremely simple structure of the proposed IA leads to a wide bandwidth and robust performance against mismatches and parasitic capacitances. Of more interest is that the differential-mode gain of the proposed IA can be electronically varied by control voltages. Post-layout and pre-layout simulation results based on 0.18[Formula: see text][Formula: see text]m TSMC CMOS parameters are included to confirm the validity of the theoretical analysis. Despite extremely simple structure, its input and output impedances are 1.93 and 1.68[Formula: see text]k[Formula: see text], respectively. Time domain analysis shows that for an input signal of 20[Formula: see text][Formula: see text]A peak to peak, maximum value of THD is 4.5% for different frequencies. Monte Carlo simulation is also carried out, which proves robust performance of the proposed IA against mismatches. The required chip area is only [Formula: see text].

Minaei, Shahram (Dogus Author) -- Conference full title: 2016 39th International Conference on Telecommunications and Signal Processing, TSP : June 27-29, 2016, Vienna, Austria. A New CMOS resistor based current mirror with extremely low voltage requirement at input (in the range of a few mV) and output voltage requirement of about one Vds is presented. The proposed structure combines the advantages of wide input swing, wide output swing, large output impedance, low input impedance and high linearity altogether, which make it attractive for high performance low-voltage and low power applications. Pspice simulations show a very low THD of -42.2dB from a single 0.9V supply in 0.18μm, input impedance of 239Ω, output impedance of 1.2MΩ and power dissipation of only 180μW. Interestingly, the input and output voltage requirements are only 10mV and 0.1V respectively.

In this paper, a novel topology for implementing resistor-free current-mode instrumentation amplifier (CMIA) is presented. Unlike the other previously reported instrumentation amplifiers (IAs), in which input and/or output signals are in voltage domain, the input and output signals in the proposed structure are current signals and signal processing is also completely done in current domain benefiting from the full advantages of current-mode signal processing. Interestingly the CMRR of the proposed topology is wholly determined by only five transistors. Compared to the most of the previously reported IAs in which at least two active elements are used to attain high common-mode rejection ratio (CMRR) resulting in a complicated circuit, the proposed structure enjoys from an extremely simple circuit. It also exhibits low input impedance employing negative feedback principal. Of more interest is that, using simple degenerate current mirrors, the differential-mode gain of the proposed CMIA can be electronically varied by control voltage. This property makes it completely free of resistors. The very low number of transistors used in the structure of the proposed CMIA grants it such desirable properties as low-voltage low-power operation, suitability for integration, wide bandwidth etc. SPICE simulation results using the TSMC 0.18-mu m CMOS process model under supply voltage of +/- 0.8 V show a high CMRR of 91 dB and a low input impedance of 291.5 Omega for the proposed CMIA. Temperature simulation results are also provided, which prove low temperature sensitivity of the proposed CMIA.

In this letter, a new voltage-mode (VM. Configuration for providing low-power and simultaneous realization of first-order low-pass, high-pass and all-pass filters is presented. The output of the all-pass filter is taken differentially. The proposed circuit contains low number of components, i.e., only two NMOS transistors, a floating battery, a grounded capacitor and a floating resistor. Adding two NMOS transistors to the proposed circuit it is modified as an all-pass filter with a single-ended output. The main advantage of the presented circuits in comparison with other counterparts is their extremely low power dissipation. Moreover, the floating resistor can be replaced with an additional NMOS transistor in triode region to provide electronic tunability. Simulation results using SPICE program are given to demonstrate the performance of the proposed circuit. © 2011 Springer Science+Business Media, LLC.

In this paper, a new voltage-mode (VM) first-order phase shifter (all-pass filter) employing only four NMOS transistors and minimum number of passive elements (i.e. one resistor and one capacitor) is proposed. The proposed VM phase shifter has high input impedance and does not require passive element matching constraints. Moreover, since only two NMOS transistors are stacked between positive and negative supply voltages, the proposed circuit is suitable for low-voltage operation. Electronic tunability can be provided easily by replacing the employed resistor with an NMOS transistor operating in triode region. Simulation results based on 0.18 μm TSMC CMOS parameters with ±0.9 V supply voltages are given to demonstrate the performance of the proposed phase shifter. © Springer Science+Business Media, LLC 2011.

In this paper, a novel design for realizing a voltage-mode (VM) all-pass filter utilizing two differential voltage current conveyors (DVCCs) is proposed. Also, the suggested filter uses a canonical number of passive elements (one grounded capacitor and one resistor) without requiring any element matching condition. The proposed filter has high input and low output impedances, which make it suitable for cascading. The effects of the nonidealities of the DVCCs on the proposed design are investigated. As an application, a quadrature oscillator is designed using the proposed VM all-pass filter and an integrator. The proposed filter and oscillator circuits are simulated using the SPICE simulation program to confirm the theory.

Operational transconductance amplifiers (OTAs) are widely used in the design of electronically tunable circuits. However, electronic tunability ranges of the OTA based filters are restricted by the limited bandwidth of the transconductance gain of the OTA. Furthermore, stability conditions and the linearity of the OTA which depends on the control current restrict the tunability. In this paper, some trade-offs in the electronically tunable filters are investigated. In addition, the tunability ranges of some first and second order OTA-C and OTA-RC filters are comparatively examined. Moreover, an OTA-C all-pass filter circuit is presented. SPICE simulations are performed and stability analyses are given for both of the OTA-C and OTA-RC filters. Operation of the presented all-pass filter is verified experimentally.

In this paper, an active network simulating mutually coupled inductors employing four second-generation current controlled conveyors, five resistors, and only two grounded capacitors is presented. The primary, secondary, and mutual simulated inductances of the circuit are independent and can be electronically tuned. The proposed circuit represents a synthetic transformer and has a positive mutual inductance. As an application, the proposed transformer is used to construct a stagger-tuned filter. Simulation Program with Integrated Circuit Emphasis (SPICE) simulation and experimental results are given to verify the theoretical analysis. © 2008 IEEE.

Yıldız, Merih (Dogus Author) -- Minaei, Shahram (Dogus Author) In this paper an NMOS based sinusoidal oscillator is presented. The circuit is constructed with voltage-mode (VM) NMOS-based analog adder and subtractor circuits which respectively perform V1+V2 and V1-V2 operations on the input voltages. The most important feature of the proposed circuits is their extremely simple structures containing only twelve NMOS transistors (six for the adder, six for the subtractor). Another significant advantage of the proposed circuits is that no external passive components are being used. The post-layout simulations of the proposed oscillator circuit have been executed using TSMC 0.25 μm process parameters with ±1.25 V power supply voltage.

Minaei, Shahram (Dogus Author) -- Göknar, İzzet Cem (Dogus Author) -- Conference full title: European Conference on Circuit Theory and Design, ECCTD 2015; Trondheim; Norway; 24 August 2015 through 26 August 2015 In this paper, a new RC circuit realization of voltage-mode (VM) first-order all-pass filter (APF) is presented. The proposed VM APF scheme is composed of a single grounded capacitor, three resistors with one being negative. The main advantage of the circuit is the common ground terminal between the input and the output. For proper functionality passive element matching is required and the negative resistance is implemented with Arbel-Goldminz operational transconductance amplifier. The theoretical results are verified with SPICE simulations using PTM 90 nm level-7 CMOS process BSIM3v3 parameters. Institute of Electrical and Electronics Engineers Inc.

Minaei, Shahram (Dogus Author) -- Conference full title: 2015 38th International Conference on Telecommunications and Signal Processing, TSP 2015; Prague; Czech Republic; 9 July 2015 through 11 July 2015 Applications of a CMOS squaring circuit in analog signal processing is studied in this paper. The circuit is based on the dual translinear loop and square-law characteristic of MOS transistor in saturation region. The reconfigurable circuit is employed as a basic analog cell for the implementation of several building blocks including multiplier, logarithmic, divider and exponential function generator circuits. It is proposed a solution for implamentation of the analog logarithmic and exponential functions, which are not an easily accessible characteristic in CMOS technology, as well as their integration in a configurable cell. Current-mode implementation of the circuits leads to straightforward and intuitive configurations. To study the performance of the circuit, effects of channel-length modulation as well as the mismatch in the threshold voltages are thoroughly discussed. The proposed circuits are designed and simulated using HSPICE simulator by level 49 parameters (BSIM3v3) in 0.35 μm standard CMOS technology. MATLAB results validate the simulation results which are obtained by HSPICE.

Minaei, Shahram (Dogus Author) -- Conference full title: 2015 38th International Conference on Telecommunications and Signal Processing, TSP 2015; Prague; Czech Republic; 9 July 2015 through 11 July 2015 In this paper, basic transconductor composed of only p-channel and n-channel metal-oxide-semiconductor field-effect transistors (MOSFETs) and its utilization for low-voltage first-order voltage-mode (VM) all-pass filter (APF) design is studied. For initial filter design a general structure employing single transconductor and two admittances was proposed. By choosing passive components and considering real behavior of MOSFETs, i.e. parasitic capacitances and output resistances, six specific cases for VM APF design are discussed. SPICE simulations using IBM 0.13 μm level-7 SIGE013 CMOS process BSIM3v3.1 parameters and with ±0.75 V supply voltages are included to support the theoretical results. The selected solution was designed at pole frequency of 219 MHz and consumes 480 μW power.

Minaei, Shahram (Dogus Author) -- Göknar, İzzet Cem (Dogus Author) -- Conference full title: IEEE International Symposium on Circuits and Systems, ISCAS 2015; Lisbon; Portugal; 24 May 2015 through 27 May 2015 In this paper, a new realization of a fully-differential (F-D) first-order all-pass filter (APF) operating in current mode (CM) is presented. In the proposed F-D CM APF a single adjustable current amplifier (ACA) and two current followers (CFS) with non-unity gain are used as active building blocks. Considering the input intrinsic resistance of CFS as useful active filter parameter, the proposed filter employs only a floating capacitor as external passive component. The pole frequency of the proposed resistorless circuit can be tuned via mutual change of input intrinsic resistance of CFS while the filter pass-band gain by means of gain of ACA. The theoretical results are verified by SPICE simulations, where TSMC 0.18 μm level-7 SCN018 CMOS process parameters were used.

Minaei, Shahram (Dogus Author) -- Göknar, İzzet Cem (Dogus Author) -- Yıldız, Merih (Dogus Author) In this paper, novel voltage-mode (VM) n-channel metal-oxide semiconductor (NMOS) transistor-based analogue adder and subtractor circuits, which, respectively, perform V1+V2 and V1−V2 operations, are presented. The most important feature of the proposed circuits is their extremely simple structures containing only six NMOS transistors. Further, the presented adder and subtractor circuits have high input and low output impedances, resulting in easy cascadability. The post-layout simulations of the proposed circuits have been executed using TSMC 0.25 µm process parameters with ±1.25 V. The area of the suggested circuits is approximately 30 × 13 µm2. Moreover, the topology of a generalised mutator, a versatile 4-port built with an adder and a subtractor, which acts as an ordinary mutator when properly reduced to a 2-port, is offered. A table for simulating lossless inductance, memristor, meminductor, memcapacitor and other elements under suitable termination of the 4-port is given, and three of these elements’ simulations with SPICE are also presented.

In this paper, a new simulated inductor employing two resistors, one capacitor, and only a single gain-variable third-generation current conveyor (GVCCIII) is proposed. To exhibit the performance of the proposed simulated inductor, it is used in a parallel R-L-C current-mode filter. The frequency-dependent nonideal voltage gain effects of the GVCCIII on the proposed inductor are given. The low- and high-frequency limitations of the simulated inductor are investigated in detail. The simulations performed with the SPICE program agree with the theoretical analysis. Also, the proposed circuit is tested experimentally using commercially available active devices (AD844 ICs of Analog Devices) to confirm the theory.

A novel circuit configuration for the realization of low power single-input three-output (SITO) current mode (CM) filters employing only MOS transistors are presented. The proposed circuit can realize low-pass (LP), band-pass (BP) and high-pass (HP) filter functions simultaneously at three high impedance outputs without changing configuration. Despite the other previously reported works, the proposed circuit is free from resistors and passive capacitors. Instead of passive capacitors; the gate-source capacitor of MOS transistor is used making the proposed circuit ideally suitable for integration. Compared to other works, the proposed filter has also the lowest number of transistors and lowest power consumption. The proposed circuit exhibits low-input and high-output impedances, which is highly desirable for cascading in CM signal processing. Moreover, it is center frequency can be electronically adjusted using a control current without a significant effect on quality factor (Q) granting it the highly desirable capability of electronic tunability. Transfer functions of the LP, BP and HP outputs are derived and the performance of the proposed circuit is proved through pre layout and post layout simulations at supply voltage of 1.8 V and using 0.18 μm CMOS process parameters. The power consumption and the required chip area are only 0.5 mW and 77.4 μm × 70.2 μm, respectively.

In this paper, a new trans-impedance mode single-input-three-output (SITO) filter using opamp compensation poles is presented. The proposed circuit is composed of two internally compensated operational amplifiers (OAs) and four single-output operational transconductance amplifiers (OTAs), without using any external passive elements. The proposed multifunction filter can realize lowpass, bandpass and highpass responses simultaneously all at low output impedances. No matching condition is required. The circuit is suitable for monolithic implementation either with complementary metal oxide semiconductor (CMOS) or bipolar technologies. All of active sensitivities are low. The performance of the circuit is tested using SPICE simulation program.

In this paper a new trans-impedance mode multifunction filter using only active elements is presented. The proposed circuit is composed of three internally compensated operational amplifiers (OAs) and three single-output operational transconductance amplifiers (OTAs), without using any external passive elements. The proposed multifunction filter can realize lowpass, bandpass and highpass responses simultaneously. No matching condition is required. The circuit is suitable for monolithic implementation either with CMOS or bipolar technologies. All of active sensitivities are low. The performance of the circuit is tested using SPICE simulation program.

In this paper a new current-mode integrator and a first order all-pass section are used to construct a quadrature oscillator. These circuits are composed of operational amplifiers (OAs) and operational transconductance amplifiers (OTAs), without using external passive elements. The proposed circuits are suitable for monolithic implementation either with CIVICS or bipolar technologies. All active sensitivities are low. The performances of the circuits are tested using a SPICE simulation program.

In this paper new voltage-mode and current-mode multifunction filters using internally compensated operational amplifiers (OP-AMPs) and single output operational transconductance amplifiers (OTAs) are presented. The proposed voltage mode multifunction filter can realize lowpass, bandpass, highpass responses simultaneously and the current-mode multifunction filter can realize lowpass, bandpass, highpass and bandstop responses simultaneously all at high output impedances. No external passive elements are required thus the circuit is suitable for monolithic implementation either with CMOS or bipolar technologies. All of active sensitivities are low. The performances of the circuits are tested using SPICE simulation program.

In this paper, a CMOS resistor-based current mirror (RBCM) aimed to be used in low-voltage applications is presented. The main features of the proposed current mirror are very low input voltage requirement (a few mV), low output voltage requirement, high output impedance and simple circuitry. The core structure of the proposed RBCM consists of three transistors (excluding bias circuitry) and two low value grounded resistors. The proposed circuit alleviates the need for cascode structures which are conventionally used to boost the output impedance and linearity. SPICE simulations using 0.18[Formula: see text][Formula: see text]m CMOS technology parameters under supply voltage of 0.9[Formula: see text]V are reported which show input and output voltage requirements of 40[Formula: see text]mV and 0.1[Formula: see text]V respectively, low THD of 1.2%, [Formula: see text] of 496[Formula: see text][Formula: see text], [Formula: see text] of 1[Formula: see text]M[Formula: see text], [Formula: see text]3[Formula: see text]dB bandwidth of 181[Formula: see text]MHz and power dissipation of 154[Formula: see text][Formula: see text]W. A high CMRR differential amplifier and a high performance current difference circuit as applications of the proposed RBCM are given. The proposed RBCM is very useful in tackling restrictions of modern technologies such as reduced supply voltage and transistors low intrinsic output impedance.

In this paper time delay calculations for current-mode circuits are considered and equivalent circuit models for delay estimation are developed. Three different equivalent circuit structures for the Core Circuit used in the multipurpose IC DU-TCC1209 are examined separately; however the relation obtained for the time delay can be applied to any CMOS current-mode circuit. The proposed calculation methods are verified with SPICE using 0.35 μm TSMC MOSIS technology parameters and with bench-test measurements using DU-TCC1209.

Conference: 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) -- Location: College Station, TX -- Date: AUG 03-06, 2014 In this paper, a new realization of a first-order voltage-mode (VM) All-Pass Filter (APF) using a grounded capacitor, three resistors, and a single Current Follower (CF) with non-unity gain is presented. The number of external resistors in the proposed VM APF can be reduced to two by considering the input intrinsic resistance of the CF as a useful active parameter. In comparison to the second-generation current conveyor-based current follower implementations employing large number of metal-oxide-semiconductor field-effect transistors (MOSFETs), here the used CF is composed of only four MOSFETs. Hence, it is favorable for low-voltage low-power circuit design. The APF was designed at pole frequency of 9.8 MHz with 112 mu W power consumption using PTM 90 nm level-7 CMOS process BSIM3v3 parameters and with +/- 0.5 V DC voltages. SPICE simulation results are included to support the theory. IEEE; IEEE Circuits & Syst Soc; Texas A & M Univ.

Conference: 57th IEEE International Midwest Symposium on Circuits and Systems (MWSCAS) -- Location: College Station, TX -- Date: AUG 03-06, 2014 -- Sponsor(s): IEEE; IEEE Circuits & Syst Soc; Texas A & M Univ In this paper, using newly introduced analog adder and subtractor circuits, a new negative impedance converter, a lossy inductor simulator and an all-pass filter structure are presented. The proposed configurations have very simple structures containing only one or two adder/subtractor blocks together also with one or two passive elements. All capacitors used are grounded which is beneficial from the integrated circuit point of view and absorption of parasitic capacitors of the active blocks. The non-ideal analyses for all of the proposed circuits are given. Design examples for realizing 10 mH inductances are presented and tested with SPICE. The simulations are based on level 49 TSMC 0.25 mu m process parameters. The designed inductances show good performance between a few ten kHz to a few MHz. In addition inverting and non-inverting all-pass filter examples providing 90 degree phase shift at 790 kHz are given. The presented all-pass filters have high-input and low-output impedances resulting in easy cascadability. Frequency responses of the proposed all-pass filters are simulated to verify the theoretical analysis. IEEE; IEEE Circuits & Syst Soc; Texas A & M Univ.

In this work, a new CMOS based grounded voltage controlled positive resistor (GVCPR) with one control voltage is proposed. The proposed GVCPR employs only five CMOS transistors, one operated in triode region and others operated in saturation region or OFF. One of the main properties of the proposed GVCPR is its ultra low power consumption; however, a single active component matching condition is needed. A number of SPICE simulation results using IBM 0.13 μm SIGE013 level-7 CMOS process parameters such as its performance analysis and verification in tunable voltage-mode first-order all-pass filter and high-Q & high-gain voltage-mode multiple-feedback second-order band-pass filter are included to confirm the theory. The superior performance of the proposed GVCPR is also proven by numeric Figure of Merit calculation. DOI: http://dx.doi.org/10.5755/j01.eee.20.7.8023

In this paper, a new grounded inductor simulator employing two current feedback operational amplifiers (CFOAs), three resistors and one grounded capacitor which is suitable for IC fabrication is proposed. Also, a new voltage-mode (VM) universal filter with three input and single output is given as application example of the grounded inductor simulator. The universal filter with low output impedance can be easily cascaded with other VM circuits. Both of the proposed circuits have the feature of improved low frequency performances, and can be easily constructed by two commercially available active devices such as AD844s. However, both inductor simulator and universal filter need a single passive component matching condition. Simulation and experimental test results are given to demonstrate the performance and workability of the proposed grounded inductor simulator and filter structure. © 2017 World Scientific Publishing Company.