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Spintronics-based devices and circuits attract massive research interest from both academia and industry. A number of the devices and logic circuits have been proposed such as spin-based magnetic tunnel junction and all spin logic gate. A fundamental spin-based device, spin field-effect transistor (spin-FET) is one of the most interesting spin-based devices to address the power issue of semiconductor transistors which is still a research focus. In this paper, we first present an electrical model for the spin-FET based on both theoretical and experimental results. The theories of spin injection and detection are considered by a current driver of the spin-FET. Gate voltage modulation following Datta–Das theory is combined with the experimental results from several works of literature. Afterward, through the dc analysis of two spin-FETs with different channel materials, we demonstrate that the channel using InAs is a better choice to make a feasible spin-FET. The channel length is also optimized by the comparison of simulation results. Finally, a local geometry spin-FET model suitable for logic design is implemented with Verilog-A language and integrated on Cadence platform. Using our model, a low-power inverter is designed based on the concept of complementary spin-FET, and a logic circuit is proposed to implement AND and NOR logic functions. Simulation results validate the behaviors of the logic circuits and availability of our model.

We present multi-function microelectromechanical systems (MEMS) logic device that can perform the fundamental logic gate AND, OR, universal logic gates NAND, NOR, and a tristate logic gate using mixed-frequency excitation. The concept is based on exciting combination resonances due to the mixing of two or more input signals. The device vibrates at two steady states: a high state when the combination resonance is activated and a low state when no resonance is activated. These vibration states are assigned to logical value 1 or 0 to realize the logic gates. Using ac signals to drive the resonator and to execute the logic inputs unifies the input and output wave forms of the logic device, thereby opening the possibility for cascading among logic devices. We found that the energy consumption per cycle of the proposed logic resonator is higher than those of existing technologies. Hence, integration of such logic devices to build complex computational system needs to take into consideration lowering the total energy consumption. [2017-0041]

As a first step to develop a diamond integrated circuit, hydrogenated diamond not and nor logic circuits composed of depletion-mode (D-mode) and enhancement-mode (E-mode) metal–oxide–semiconductor field-effect transistors (MOSFETs) are fabricated. The D- and E-modes MOSFETs act as load and driver devices for the logic circuits, respectively, which provides complementary transistor actions. The extrinsic transconductance maxima for both the MOSFETs are almost the same value of 17 mS mm $^{-1}$ and insensitive to device processing. With supply voltage changing from −5 to −25 V, gain maximum for not logic circuit increases from 1.2 to 26.1. The nor logic circuit shows clear nor gate characteristics.

A new unipolar differential logic (UDL) for the large-scale integration of amorphous In-Ga-Zn-O (aIGZO) digital circuits is proposed. Only single-threshold single-gate and aIGZO thin-film transistors are required. The proposed UDL logic gates are very insensitive to transistor parameter variations (i.e., threshold voltage, mobility, off-current, and subthreshold slope), which are inherently due to large-area low-temperature fabrication processes and operating conditions. To assess the UDL effectiveness, a wide range of parameter variations is considered: and, owing to the proposed architecture up to 1.5 $\times$ 107 UDL gates that can be integrated with a yield that is greater than 90%.

Micro/nano-electromechanical resonator based logic computation has attracted significant attention in recent years due to its dynamic mode of operation, ultra-low power consumption, and potential for reprogrammable and reversible computing. Here we demonstrate a 4-bit parity checker circuit by utilizing recently developed logic gates based on MEMS resonators. Toward this, resonance frequencies of shallow arch shaped micro-resonators are electrothermally tuned by the logic inputs to constitute the required logic gates for the proposed parity checker circuit. This study demonstrates that by utilizing MEMS resonator based logic elements, complex digital circuits can be realized.

In this paper, we describe a new approach to reduce dynamic power, leakage, and area of application-specified integrated circuits, without sacrificing performance. The approach is based on a design of threshold logic gates (TLGs) and their seamless integration with conventional standard-cell design flow. We first describe a new robust, standard-cell library of configurable circuits for implementing threshold functions. Abstractly, the threshold gate behaves as a multi-input, single-output, edge-triggered flip-flop, which computes a threshold function of the inputs on the clock edge. The library consists of a small number of cells, each of which can compute a set of complex threshold functions, which would otherwise require a multilevel network. The function realized by a given threshold gate is determined by how signals are mapped to its inputs. We present a method for the assignment of signals to the inputs of a threshold gate to realize a given threshold function. Next, we present an algorithm that replaces a subset of flip-flops and portions of their logic cones in a conventional logic netlist, with threshold gates from the library. The resulting circuits, with both conventional and TLGs (called hybrid circuits), are placed and routed using commercial tools. We demonstrate significant reductions (using postlayout simulations) in power, leakage, and area of the hybrid circuits when compared with the conventional logic circuits, when both are operated at the maximum possible frequency of the conventional design.

The in situ logic operation on memristor memory has attracted researchers' attention. In this brief, a new circuit structure that performs a stateful OR logic operation is proposed. When our OR logic is operated in series with other logic operations (IMP, AND), only two voltages should to be changed while three voltages are necessary in the previous one-step OR logic operation. In addition, this circuit structure can be extended to multi-inputs OR operation to perfect the family of logic operations on memristive memory in nanocrossbar based networks. The proposed OR gate can enable fast logic operation, reduce the number of required memristors and the sequential steps. Through analysis and simulation, the feasibility of OR operation is demonstrated and the appropriate parameters are obtained.

NOR gate operation using organic devices was demonstrated based on resistor-transistor logic (RTL). The RTL was composed of an OR gate using two single layered devices as input resistors and a NOT gate (inverter) using a vertical-type metal base organic transistor (MBOT). The input resistors were connected to the base electrode of the MBOT. When either input was turned from low to high voltage, the output voltage changed from high to low, indicating NOR operation. Dynamic characteristics of the RTL circuit was also evaluated, and operation frequency was estimated to be 300 Hz.

The modulation of current through an electrostatically formed nanowire (EFN) is controlled by the voltage on the four input gates. The behavior of this multi-gate transistor can be interpreted as a complex four-input switching process, enabling the computation of multiple-input threshold logic functions using a single device. We have therefore created a novel threshold logic family leveraging these unique capabilities that enables the efficient computation of complex logic functions. Experimental and simulation data are provided to demonstrate feasibility and evaluate behavior. This logic family overcomes the challenge posed by the input-output voltage mismatch inherent to EFNs and produces circuits with one-eighth the number of active logic devices and one-quarter the number of transistors required by CMOS.

This paper introduces two new cells for logic-in-memory (LiM) operation. The first novelty of these cells is the resistive random access memory configuration that utilizes a programmable metallization cell as nonvolatile element. CMOS transistors and ambipolar transistors are used as processing and control elements for the logic operations of the LiM cells. The first cell employs ambipolar transistors and CMOS in its logic circuit (7T2A1P), while the second LiM cell uses only MOSFETs (9T1P) to implement logic functions, such as AND, OR, and XOR. The operational mode of the proposed cells is voltage-based, which is much different from the previous designs in which a LiM cell operates on a current mode. Extensive simulation results using HSPICE are provided for the evaluation of these cells; comparison shows that the proposed two cells outperform previous LiM cells in metrics, such as logic operation delays, power delay product, circuit complexity, write time, and output swing.

Testability is a major concern in industry for today’s complex system-on-chip design. Design-for-testability (DFT) techniques are essential for any logic style, including asynchronous logic styles in order to reduce the test cost. Sleep convention logic (SCL) is a new promising asynchronous logic style that is based on the more well-known asynchronous logic style NULL convention logic (NCL). In contrast to the NCL, there are currently no design for testability methodologies existing for the SCL. The aim of this paper is to analyze the various faults within SCL pipelines and propose a scan-based DFT methodology to make the SCL testable. The proposed DFT methodology is then validated through a number of experiments, showing that the methodology provides a high test coverage (>99%). The complete DFT methodology as well as the scan chain and scan cell design are presented.

Side-channel analysis (SCA) is a powerful technique to reveal the secrets using detectable physical leakages from logic elements, which brings severe security threats to modern circuits. To alleviate this problem, applying cell-level countermeasure is usually a suitable solution, which is mainly implemented as dual-rail precharge logic. Mace et al. has the proposed dynamic current mode logic (DyCML) scheme as a novel technology to resist SCA, whose power consumption is constant regardless of the data processed. However, the DyCML-based sequential elements are still in blank field. So, we have implemented a novel flip-flop compatible with DyCML, whose enhanced security has been proved by corresponding simulations.

Multiple advanced logic circuits including the full-adder, full-subtract and majority logic gate have been successfully realized on a DNA/GO platform for the first time. All the logic gates were implemented in an enzyme-free condition. The investigation provides a wider field of vision towards prototypical DNA-based algebra logical operations and promotes the development of advanced logic circuits.

Parallel Prefix Radix 2 8 bit Comparators using Constant Delay (CD) logic is presented in this paper. The constant delay logic pre discharges the output to zero logic and switches to a logic one through a critical path clocked PMOS transistor. CD logic operation is much faster than a dynamic logic circuit during its D-Q mode of operation. The comparator's architecture consists of two stages; where the first stage uses a pass transistor pre encoding circuitry for achieving low power consumption and the second stage employs a high performance dynamic-CD-static logic manner combination comparators. Design and simulation were carried out in Mentor Graphics ELDO Simulator using 180 nm technology.

Programmable logic devices on base of asynchronous combinational circuits with feedback are considered. The main aim of the research is to obtain a method for designing a circuit with a set of prescribed stable states or a circuit without stable states — a generator of true random numbers. Both the cases of binary and ternary logics are studied.

We report on the fabrication and characterization of entirely screen-printed integrated logic circuits based on organic electrochemical transistors on flexible poly(ethylene terephthalate) (PET) substrates. The transistors are based on poly(3,4-ethylenedioxithiophene) poly(styrenesulfonate) and operate at a voltage of 1.5 V. Together with screen-printed resistors, the printed transistors were used as the building blocks for inverters, NAND gates, flip-flops, and a 2-b shift register. Dynamic characterizations of these logic gates need only five different inks that reveal a high reproducibility of the measured devices’ output signals. These results clearly indicate the high uniformity and reproducibility of the screen-printed transistors and resistors, emphasizing their applicability for integrated circuitry.

A new benchmarking of beyond-CMOS exploratory devices for logic integrated circuits is presented. It includes new devices with ferroelectric, straintronic, and orbitronic computational state variables. Standby power treatment and memory circuits are included. The set of circuits is extended to sequential logic, including arithmetic logic units. The conclusion that tunneling field-effect transistors are the leading low-power option is reinforced. Ferroelectric transistors may present an attractive option with faster switching delay. Magnetoelectric effects are more energy efficient than spin transfer torque, but the switching speed of magnetization is a limitation. This article enables a better focus on promising beyond-CMOS exploratory devices.

Single electron technology is an attractive technology for future low-power VLSI/ULSI systems. Single electronics implies the possibility to control the movement and position of a single electron or a small amount of electrons. In this work, design, implementation, and analysis of logic functions are presented using single electron threshold logic gate (TLG) and hybrid SET-MOS circuits. The logic operation of the designed circuit is tested using Monte Carlo-based simulation tool SIMON for the single electron threshold logic circuit. For the hybrid SET-MOS-based implementation, the logic operation of the circuit is verified in Tanner environment. A compact analytical model with 11 island states for SET devices and BSIM4.6.1 model for MOS is used. The influence of thermal fluctuation on the stability of the threshold logic-based circuit, caused by increase in system temperature, has been thoroughly investigated. The effect of island states on the performance of the hybrid SET-MOS circuit is analysed...

Soft errors can occur in digital integrated circuits (ICs) as a result of an electromagnetic disturbance, such as might result from an electrical fast transient (EFT). Many soft errors come from changes in propagation delays through digital logic, which are caused by changes in the on-die power supply voltage. An analytical model was developed to predict timing variations in digital logic as a result of variations in the power supply voltage. The derivation of the analytical delay model is reported. The model was validated experimentally by applying EFTs to a ring oscillator built in a test IC. The predicted and measured ring oscillator frequencies (or periods) agreed within a relative error of less than 2.0%. To further validate the approach, the model was applied to test the response of more complex circuits consisting of NAND/NOR logic gates, binary adders, dynamic logic gates, and transmission gates. The circuits were fabricated on a 0.5 μm test IC and simulated on two additional process technologies (0.18 μm and 45 nm). The model performed well in each case with a maximum relative error of 5.6%, verifying the applicability of the model for analyzing complex logic circuits within a variety of process technologies. The proposed delay model can be used by IC design engineers to predict and understand the change in the propagation delay through logic circuits due to the disturbed power supply.

This brief proposes a logic gate that performs a stateful or logic operation on memristor memory. The presented logic structure concurrently executes an or operation in the nanocrossbar architecture in a single step, which enables a fast logic operation and reduces the number of required memristors. The proposed circuit completes the in situ logic operation on the memristor memory, which alleviates the burden of the processor significantly. Through analysis and simulation, the feasibility of the or operation is demonstrated, and the parameter optimization is analyzed.

is a very useful combinational logic circuit. In this paper performance analysis of CMOS Comparator and PTL logic design has been shown. In the design of integrated circuits, several logic families is being used which is described by Pass Transistor Logic (PTL). It reduces the count of transistors used to make different logic gates, by eliminating redundant transistors. The layout of 2-bit comparator is developed using automatic and semi-custom techniques. Both the layouts are compared and analyzed in terms of their area consumption. Automatic layout is generated from its equivalent schematic whereas semi-custom layout is optimized manually. The result shows that semi- custom layout of PTL logic consumes 35% less area as compared to CMOS logic design to provide area efficient solution. Keywordstechnology, Layout, Performance analysis, logic circuits, PTL

In this paper, a detailed analysis and comparison of nanoelectromechanical systems (NEMS) and CMOS technologies for low power adiabatic logic implementation is presented. Fundamental limits of CMOS-based adiabatic logic are identified. Analytic relations describing the energy-performance for sub-threshold adiabatic logic are also explicitly derived and optimized. The interest of combining NEMS technology and adiabatic logic is described, and the key NEMS switch parameters that govern the dissipation-performance relationship are identified as the switch commutation frequency, its actuation voltage, and the contact resistance between the switch electrodes. Furthermore, NEMS-based adiabatic gates architectures are described. Finally, the contribution of the power-clock or energy recovery generator is estimated in order to compare CMOS and NEMS-based adiabatic architectures at the system level. The paper concludes with a detailed comparison of the energy-performance of the different explored technologies.

A tribotronic logic device is fabricated to convert external mechanical stimuli into logic level signals, and tribotronic logic circuits such as NOT, AND, OR, NAND, NOR, XOR, and XNOR gates are demonstrated for performing mechanical-electrical coupled tribotronic logic operations, which realize the direct interaction between the external environment and the current silicon integrated circuits.

The spatial wave-function switched field-effect transistor (SWSFET) has two or three low bandgap quantum well channels that can conduct carrier flow from source to drain of the SWSFET. Because of this property, SWSFETs are useful to implement different multivalued logic with reduced device count. In this paper, we introduce the circuit model of a SWSFET and the design of a unipolar inverter where only one kind of charge carrier contributes to the current flow. We also simulate two input unipolar logic gates such as NAND and NOR and demonstrate their universal property to implement other unipolar logic gates. We also simulate NOR gate and full adder circuits based on unipolar logic gates.

The cascading of logic gates is a critical challenge for the development of spintronic logic circuits. Here we propose the first logic family exploiting magnetoresistive bipolar spin-transistors to achieve a complete spintronic logic family in which logic gates can be cascaded. This logic family, emitter-coupled spin-transistor logic (ECSTL), is an extension of emitter-coupled logic (ECL) that leverages the advanced features of spintronic devices. The current through the ECL differential amplifier is routed to create a magnetic field that modulates the magnetoamplification of the spin-transistors. This cascading mechanism supplements the voltage cascading available in conventional ECL, providing additional inputs to each logic stage. Each gate therefore has increased logical functionality, leading to logic minimization and compact circuits. No additional current is required to employ this added spintronic switching, resulting in improved speed, area, and power characteristics. This logic family achieves a power-delay product 10–25 times smaller than conventional ECL, inspiring a pathway for high-performance spintronic computing beyond 10 GHz.

Single electron transistors (SETs) have ultra-small size, ultra-low power dissipation and unique Coulomb blockade oscillation characteristics which make them promising candidates for future technologies. However, SETs have extremely poor driving capabilities, low gain and background charges effect so that direct application to practical circuits is as yet almost impossible. A hybridization of existing CMOS technology with SETs is to overcome SET drawbacks and to investigate the robustness and fastness of the novel design in comparing with existing CMOS technology. The main objectives of this paper are to establish standard design styles for hybrid SET---CMOS logic circuits, and to propose a new static differential design style with superior performance at room temperature. This paper provides new SET---CMOS logic gates based on the differential design style, and also demonstrates the comparative performance study of full-adder circuits based on various SET---CMOS design styles. The comparison shows that the proposed differential logic circuit achieves a greater significance performance upon other SET---CMOS logic circuits. The final conclusion is made that the differential SET---CMOS style is more attractive design methodology for next generation VLSI/ULSI circuits.

A voltage-mode three transistor based MAX circuit for implementation of multi-valued logic (MVL) system is proposed in this paper. The proposed MAX operates at very low power consumption ranging in micro watts. To evaluate MAX performance, a NOR gate realization is done and compared to standard CMOS NOR gate. The HSpice simulation result confirms the MAX based NOR gate to operate with minimal delay at low power level. The simulations have been performed on 180 nm technology.

The article considers the fundamentals of logical synthesis of digital nodes of electronic computer on base of current realization of threshold logic. The examples of logical and circuit description of combinational and sequential logical elements and the results of their computer simulation are given. It is concluded that the proposed approach to the threshold synthesis of digital structures in current logic is promising.

Memristor is considered as one of the promising solutions to the fundamental limitations of the VLSI systems. Logic implementation with memristor device by considering its compatibility with CMOS fabric provides a new vision for digital logic circuits. This work presents a 2 by 2 multiplier cell design using a hybrid CMOS-memristor universal gate. The universal gate based implementation approach is the extension for memristor ratioed logic (MRL) with lower implementation cost. Simulation results confirm functionality of the proposed circuit. This circuit requires 16 memristors, 8 transistors and only one computational time step for multiplication. Compared with previous works, this approach presents considerably lower implementation cost.

Thin-film transistor (TFT) circuits are important for flexible electronics which are promising in the area of wearable devices. However, most TFT technologies only have unipolar devices and the process variation and defective rate are relatively high, which impose challenges to TFT circuit design. In this paper, we propose a novel logic array based on pseudo-CMOS logic to address the problem of unipolar TFT circuit design. A multi-layer interconnect architecture and wire routing methodology are presented to improve the routability and meanwhile the area efficiency. The experimental results show that the proposed logic array reduces more than 80% area compared with transistor level scheme.

Spintronic devices have the potential to lower the power consumption of computing architectures such as Arithmetic Logic Units (ALUs). However, the existing spintronic ALUs still rely on charge current, which doesn't allow exploiting the spin devices properties for information transmission. All Spin Logic (ASL) devices based circuits have the potential to further improve these circuits and systems since they rely on pure spin current. Indeed, it has been shown that ASL-based circuits can be reconfigured through modification of the injection current polarity and the states of the control terminals. In this paper, for the first time, we propose two one-bit ALUs implemented using ASL devices. The first ALU is designed by the assembly of logic circuits while the second ALU is synthesized using majority gate method. SPICE simulations have been carried out with 40 nm diameter MTJ and the ALUs are compared regarding energy consumption and the number of ASL devices metrics. Comparison results show that the ALU designed using a majority gate based synthesis method consumes more energy than the logic circuit based ALU (1.917 vs. 0.486 nJ) but is easier to control.

In this paper we propose a novel approach for designing digital circuits that uses the variance of a signal to represent Boolean logic levels. The variance-based logic (VBL) representation enables embedding of rectification and multiplication modules within the basic logic cells and unlike AC-coupled or energy-recovery logic circuits the proposed approach obviates the need for any phase synchronization. As a result, VBL representation can be used for designing low-latency digital circuits that are directly powered by a combination of energy transducers with different frequency and source impedance characteristics. We present some representative examples of VBL circuits that can be implemented in a standard CMOS process and we present measurement results from fabricated prototype.

Implementations of polynomials and functions using stochastic logic have been of interest due to their low-area and high fault-tolerance properties. In stochastic logic, numbers are represented using unary bit streams where each bit is of same weight. If a number is represented in the range [0,1], the representation is referred to as unipolar. The representation is referred as bipolar if the number lies in the range [−1, 1]. Typically, inputs and outputs are in same format. However, sometimes the input and output may be in different formats; these are referred as circuits using hybrid formats. While analysis of unipolar stochastic logic circuits and bipolar logic circuits containing ex-or, ex-nor and multiplexors are well understood, the analysis of general bipolar stochastic logic circuits and hybrid logic circuits are not well understood. This paper presents general approaches to compute outputs of bipolar and hybrid stochastic logic circuits. It is shown that the analysis approach presented in this paper can form a basis for synthesis of stochastic logic circuits in bipolar and hybrid formats.

Current through ambipolar carbon nanotube field-effect transistors (CNTFETs) can be controlled by two independent gates, enabling highly expressive XOR-based logic circuits. To promote efficient circuit design, it is important to develop an easy-to-use SPICE-compatible model for these dualgate ambipolar CNTFETs. This paper therefore introduces a closed-form model that matches the experimentally demonstrated behavior. This model is then applied for the first simulation of cascaded dual-gate CNTFET logic circuits that exploit ambipolarity for compact logic.

Benefitting from its non-volatility, low power, high speed, nearly infinite endurance, good scalability and great CMOS compatibility, magnetic tunnel junction (MTJ) embedded in conventional CMOS logic circuits has been proposed as one potentially powerful solution to introduce non-volatility in today's programmable logic circuits, which is envisioned to extend the Moore's law [1].

CMOS and nano-electromechanical (NEM) hybrid reconfigurable logic (RL) circuits are implemented by using monolithic three-dimensional (M3D) integration process. Their operation and feasibility are discussed based on simulation and experimental results.

With advent of technology scaling, the prime objective of design i.e. low power consumption can be easily acquired. For any digital logic design the power consumption depends on; Supply voltage, number of transistors incorporated in circuit and scaling ratios of the same. As CMOS technology supports inversion logic designs; NAND & NOR structures are useful for converting any logic equation into physical level design that comprises of PMOS and NMOS transistors. In similar way, logic can be implemented in other styles as well, with the difference in number of transistors required. The conventional CMOS design for XOR logic can be possible with 8 or more than 8 transistors, with the methodology discussed in this paper, the same design for XOR logic can be made possible with 6 transistors. The proposed methodology consists of Pass transistor logic and Single feedback topology. This design consumes 50% less power than that of conventional XOR logic design with CMOS technology. Since the design for XOR logic, is useful for variety of applications such as Data encryption, Arithmetic circuits, Binary to Gray encoding etc. the XOR logic has been selected for design. The design explained in this paper is simulated with Cadence 90nm technology.

We implement a dynamic logic gate which consists of three elements: a chaotic fiber laser, a threshold controller and the output of the logic gate. The output signal of the fiber laser is sent to the logic gate input as to the threshold controller; threshold controller output signal is sent at the entrance of the logic gate and also feedback to the fiber laser which changes their dynamic behavior. The output of the logic gate consists of a difference amplifier; this compares the signals sent by the threshold controller and the fiber laser, resulting logic output that depend on an accessible parameter in threshold controller. We present the numerical results and experimental of the implementation of a dynamic logic gate using fiber laser, which demonstrates the ability to change the type of logic gate by modifying a parameter of threshold control.

Continued scaling of bulk CMOS technology is facing formidable challenges. FinFETs, with better control of short-channel effects, offer a promising alternative for the 22-nm technology node and beyond. However, FinFETs still suffer from process, voltage, and temperature (PVT) variations. Thus, to analyze the delay of FinFET logic circuits, statistical static timing analysis (SSTA) is more suitable than traditional static timing analysis. In this paper, using an existing SSTA algorithm as a foundation, we analyze silicon-on-insulator FinFET circuits in various new ways: basing the analysis on accurate device simulation of the logic library; considering voltage and temperature variations, in addition to process variations; deriving accurate timing and leakage macromodels; and investigating the impact of PVT variations on delay/leakage distributions at the circuit level. We propose a simplified timing model that greatly reduces the computational complexity without giving rise to any convergence issues. The timing model has an average absolute error of 3.4% and 4.4%, respectively, for gate output slope and gate delay over all logic gates and sizes, compared with accurate quasi-Monte Carlo simulations. We evaluate the performance of our SSTA algorithm with respect to Monte Carlo simulation, and extend the algorithm to enable statistical leakage and dynamic power analysis as well. We investigate the impact of PVT variations on delay/power distributions at the circuit level. We show that deterministic optimization methods can optimize both the mean and variance of circuit delay/power distributions, and even the ratio of standard deviation to mean in some cases. Finally, we show that FinFET circuits need to be carefully optimized with temperature taken into consideration, since the ratio between the leakage and dynamic power of a circuit can vary drastically depending on the operating temperature assumed.

Dynamic logic style is used in high performance circuit design because of its fast speed and less transistors requirement as compared to CMOS logic style. But it is not widely accepted for all types of circuit implementations due to its less noise tolerance and charge sharing problems. A small noise at the input of the dynamic logic can change the desired output. Domino logic uses one static CMOS inverter at the output of dynamic node which is more noise immune and consuming very less power as compared to other proposed circuit. In this paper, an overview and classification of these techniques are first presented and then compared according to their performance.

Thanks to the progress in nonvolatile (NV) devices, such as magnetic tunnel junctions and phase change memories, various NV logic blocks have recently been proposed to overcome energy/delay bottlenecks caused by von Neumann computing architecture. The ferroelectric tunnel memristor (FTM) is an emerging NV multilevel device and was recently reported to show excellent performance. In this paper, we demonstrated that the short-circuit effect in an FTM provides the opportunity to design a novel FTM-based Boolean logic block. This block is composed of an FTM and a load resistor. Unlike classical schemes, where at least two cells are required as operands, our FTM-based block implements logic operation inside a single memristor. With a compact model of an FTM, transient simulation is performed to validate NAND and NOR logic functions. Finally, we provide the method of performance optimization and discuss the advantages/disadvantages of the proposed logic block to summarize our work.

In thin-film transistor (TFT) logic circuit applications, propagation delay and power dissipation are two key constraints to be considered in optimal circuit design and synthesis. The unipolar zero-V-load logic design is widely used for implementation of TFT digital circuits, because of the simple structure, easy processing, and relatively high gain. In this paper, the analytical models for delay and power were developed for zero-V-load inverters, which clarify the relationships between device and design parameters and the two key design constraints. The proposed models were verified by circuit simulations, and could serve as a guideline for optimal design of unipolar zero-V-load logic circuits.

The very high density of integration and ultra-low power consumption characteristics has given the Single electron devices promising capabilities to replace CMOS transistors in some applications. There are also alternative logic design styles, such as threshold logic, that may be more suitable and also more powerful for novel technologies such as single electron technology. In this paper, we investigate single electron threshold logic gate implementation of some logic circuits, in which the Boolean logic values are encoded as absence or presence of one electron. We present a control unit for a chemical process. Computer based realization of the control unit is performed using SIMON simulation tool. The performance of the simulated model is studied with some sample data and found satisfactory thereby establishing the feasibility of using single electron threshold logic based devices for high future high density low power VLSI/ULSI circuits.

Memristors are novel devices, useful as memory at all hierarchies. These devices can also behave as logic circuits. In this paper, the IMPLY logic gate, a memristor-based logic circuit, is described. In this memristive logic family, each memristor is used as an input, output, computational logic element, and latch in different stages of the computing process. The logical state is determined by the resistance of the memristor. This logic family can be integrated within a memristor-based crossbar, commonly used for memory. In this paper, a methodology for designing this logic family is proposed. The design methodology is based on a general design flow, suitable for all deterministic memristive logic families, and includes some additional design constraints to support the IMPLY logic family. An IMPLY 8-bit full adder based on this design methodology is presented as a case study.

This paper demonstrates the design of nanomagnetic logic (NML) gates with multiple weighted inputs, which are magnetic equivalents of threshold logic gates (TLGs). We use micromagnetic simulations to show that NML TLGs can be constructed with minimum overhead compared to standard NML gates, and they significantly reduce device footprint and interconnection complexity of magnetic logic circuits. As an example, we design a full adder circuit using said TLGs and compare its performance to majority-gate-based NML.

In this paper, the complementary and selective characteristics of ECL (Emitter-Coupled Logic) circuit are fully taken advantage to implement various logic gates including MUX, XOR, AND, NAND, OR, and so on. From the analysis, we find that one ECL circuit can realize many relative logic functions, which is more flexible than CMOS logic. We conclude that if the characteristics of ECL circuit are fully taken advantages, the design of logic functions can be very easy.

the demand of low power high performance arithmetic circuits multiplies, during this paper, we aim to introduce a style of latest MT-CMOS domino logic and FTL dynamic logic technique to style adder circuit. The MT-MOS transistors cut back the facility dissipation by minimizing sub threshold run current in the introduced domino logic circuits. The MT-NMOS semiconductor connected in discharging path of output electrical converter may be applied for pipeline structure to scale back the facility consumptions and increase fan-out. Dynamic logic vogue CMOS circuit is employed to enhance the speed and cut back the world of style by decreasing the device count. The introduced FTL dynamic logic circuit improves the performance by evaluating the computational blocks partially before its input signals are formalized and then rapidly perform a final evaluation as soon as the inputs arrive. This dynamic logic formation is like minded for an arithmetic circuit wherever the important path s created of an outsized cascade of inverting gates is created. The mixture of MT-CMOS and dynamic logic circuit provides high fan-out, high change frequencies with each lower delay and dynamic power consumption. The simulation results of those projected low power high performance circuits provide 75% power reduction, three times redoubled high speed operation and active space reduction, whereas revealing lower sensitivity to power provide, temperature, electrical phenomenon load and method variations than the dynamic domino CMOS technologies.

Programmable reversible logic is emerging as a prospective logic design style for implementation in low power, low frequency applications where minimal impact on circuit heat generation is desirable, such as mitigation of differential power analysis attacks. Adiabatic logic is an implementation of reversible logic in CMOS where the current flow through the circuit is controlled such that the energy dissipation due to switching and capacitor dissipation is minimized. Recent advances in dual-rail adiabatic logic show reduction in average and differential power, making this design methodology advantageous in applications where security is the primary design metric and operating frequency is slower, such as Smart Cards. In this paper, we present an algorithm for synthesis of adiabatic circuits in CMOS. Then, using the ESPRESSO heuristic for minimization of Boolean functions method on each output node, we reduce the size of the synthesized circuit. Our approach correlates the horizontal offsets in the permutation matrix with the necessary switches required for synthesis instead of using a library of equivalent functions. The synthesis results show that, on average, the proposed algorithm represents an improvement of 36% over the best known reversible designs with the optimized dual-rail cell libraries. Then, we present an adiabatic S-box which significantly reduces energy imbalance compared to previous benchmarks. The design is capable of forward encryption and reverse decryption with minimal overhead, allowing for efficient hardware reuse.

Multiple valued logic (MVL) circuits are particularly attractive for nanoscale implementation as advantages in information density and operating speed can be harvested using emerging technologies. In this paper, a new family of MVL gates is proposed for implementation using carbon nanotube field-effect transistors (CNTFETs). The proposed designs use pseudo N-type CNTFETs and no resistor is utilized for their operation. This approach exploits threshold voltage control of the P-type and N-type transistors, while ensuring correct MVL operation for both ternary and quaternary logic gates. This paper provides a detailed assessment of several figures of merit, such as static power consumption, switching power consumption, propagation delay and the power-delay product (PDP). Compared with resistor-loaded designs, the proposed pseudo-NCNTFET MVL gates show advantages in circuit area, power consumption and energy efficiency, while still incurring a comparable propagation delay. Compared to a complementary logic family, the pseudo-NCNTFET MVL logic family requires a smaller circuit area with a similar propagation delay on average, albeit with a larger PDP and static power consumption. A design methodology and a discussion of issues related to leakage and yield are also provided for the proposed MVL logic family.

We report on the fabrication of organic electrochemical transistors structured by nanoimprint lithography. The devices were scaled down as a result of our previous findings for inkjet printed transistors, where a reduced source-drain width and a shorter distance to the gate resulted in higher ON-to-OFF current ratios. We could show that these findings also prove true for transistors with feature sizes below 10 μm. Furthermore, we fabricated inverters and NAND gates with switching times below 1 s. These logic gates mark an important step for organic electrochemical transistors toward their usability in more complex logic circuits.