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Multiple second-order generalized integrators (MSOGI) has been widely used to extract the signal that contains multiple harmonics. The MSOGI needs to be implemented in the discrete-time domain for its practical applications. More critically, the discretization method can greatly affect its performance. The existing discretization methods for MSOGI can be divided into three categories: entire transfer-function discretization, SOGI-transfer-function discretization, and integrator discretization. The theoretical analysis indicates that the first method can avoid the errors caused by unit delay, but it is hard to be digitally realized for high-order transfer functions. The other two methods have nonnegligible errors in both the phase and the quadrature characteristic due to the unit delay. In this letter, we propose a novel discretization method by modifying the structure of integrator discretization. This method can enhance the performance in both the phase and the quadrature characteristic with an acceptable computation burden, which has been theoretically analyzed and experimentally verified. [ABSTRACT FROM AUTHOR]

No dead-time is contained in the existing dead-time elimination pulsewidth modulation (PWM) for three-phase three-level T-type converters, where complementary drive pulses are allocated alternatively according to polarities of output currents. Consequently, the dead-time effect can be inherently avoided. However, the dependency on current polarities seriously limits its widespread application. Wrong current polarities, e.g., in a dynamic process, will lead to the output-voltage disappearance, thus aggravating the possible “algebraic loop” issue and impairing the stability of the system. In this article, in order to reduce the dependency on current polarities while retaining the characteristic of dead-time-effect elimination, a double-modulation-wave PWM is proposed by modifying the dead-time elimination PWM. Two modulation waves with a magnitude difference are adopted for generating underlap periods between complementary drive pulses, which can avoid the shoot-through failure and no dead-time effect will be generated. And to further simplify the implementation process, the two modulation waves are decomposed by introducing a magnitude-adjustment factor related to the current polarity. Whereas it is also due to the employment of two modulation waves, extra issues of overmodulation, single drive pulses, and a shorter underlap period may occur, which are analyzed in detail and the negative effect can be avoided. Finally, the proposed PWM is experimentally verified, showing the effectiveness on harmonic suppression and the reduced dependency on current polarities. [ABSTRACT FROM AUTHOR]

The dead-time elimination pulsewidth modulation (PWM) enables the drive pulses of the upper and the lower switching devices to alternate according to the current polarity, thus abandoning the dead time and essentially avoiding the dead-time effect in power converters. However, the current zero crossing will be distorted by the current jump generated by the drive-pulse alternation, and the current zero-crossing distortion will be further intensified if errors exist in the detected current polarity. Thanks to the noise-attenuation and frequency-adaptability characteristics of the double second-order generalized integrator frequency-locked loop (DSOGI-FLL), it can obtain accurate current polarities even in harmonic and unbalanced conditions. A DSOGI-FLL-based dead-time elimination PWM is, therefore, proposed in this paper, and several improvements are made to minimize the current zero-crossing distortion. An underlap period is added when alternating the upper and lower drive pulses to smooth the current jump at zero crossing, and a delay compensation term is inserted in the DSOGI-FLL to compensate both the current measurement delay and the control delay. The effectiveness of the proposed DSOGI-FLL-based dead-time elimination PWM has been validated by experiments, respectively, in the unbalanced-current, power-change, and frequency-variation conditions with an RL load, as well as in a grid-connected converter. [ABSTRACT FROM AUTHOR]

Accurate flux estimation is essential for the implementation of a high-performance ac motor drive. However, it still faces some problems, which can better be projected by analyzing performances of existing flux estimators, implemented with either a pure integrator or a low-pass filter (LPF). To solve the problems, an alternative flux estimator, implemented with a single second-order generalized integrator (SOGI) and a frequency-locked loop (FLL), is discussed for induction motor drives. The SOGI block included in this algorithm works for integrating the back-electromotive force, which unlike the pure integrator and LPF, does not experience saturation and significant dc offsets caused by different initial conditions. The single-SOGI-FLL estimator does not need additional magnitude and phase compensation, while its performance may deteriorate at low speed, caused by the inverse proportional relationship between its estimated flux and the frequency. A multi-SOGI-FLL flux estimator is, thus, proposed for uncompromised attenuation of dc and harmonic errors even under low-speed condition. Excellent flux estimation can, hence, be offered over the full-speed range, as proven through theoretical studies and experiments. [ABSTRACT FROM AUTHOR]