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A hybrid cooling scheme utilizing superlattice coolers (SLCs) along with microchannel heat sink for thermal management of hotspots is presented. In this paper, we have studied the effect of operating and design parameters on the performance of the SLC. We have also experimentally investigated the effect of interface thermal resistance as well as thermal resistance between the ground electrode and superlattice using two test configurations: one with on-chip microchannels and another with off-chip microchannels. We demonstrated heat removal capability at the localized hotspots of more than over 300 W/cm2. [ABSTRACT FROM AUTHOR]

Thermal coupling between superlattice coolers (SLCs) in an array adversely affects performance of an each individual cooler compared with an isolated device. Here, we have developed an electrothermal model to study this coupling between SLCs and how it is affected by geometric parameters such as separation between the superlattice structure and a ground electrode, and operating parameters such as the convective heat transfer coefficient and the activation current applied for driving the SLC. Complementary to the modeling efforts, we have also experimentally studied thermal coupling between SLCs in a microfabricated array under various conditions. Simulation results are critically compared against the experimental data and yield the conclusions of importance for an optimized design of the hybrid microfluidic SLC cooling scheme for thermal management of multiple clustered hotspots in microprocessors. We have observed more than 60% reduction in cooler performance, when placed within the few characteristic diameters of the ground electrode, due to thermal coupling effect. Thermal properties of the working fluid have even more pronounced effect on the thermal coupling between the coolers. [ABSTRACT FROM PUBLISHER]

In this article we describe a novel cooling scheme utilizing a combination of fluidic (single-phase convection and phase change) and solid-state (superlattice cooler) techniques to simultaneously remove high background heat fluxes (∼100 W/cm2) over the entire chip and dissipate ultra high heat fluxes (∼0.5-1 kW/cm2) from multiple localized hot spots. This article focuses on the conceptual design to assess the feasibility of the proposed cooling scheme. [ABSTRACT FROM AUTHOR]