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In this article, we investigate the self-heating effect (SHE) of the Complementary FET (CFET) device and propose a cross-coupled thermal network model. For the investigation of thermal behavior, the intra- and inter-device crosstalk of CFET is evaluated qualitatively through the defined crosstalk coefficient. The results indicate that CFETs have more severe intra-device thermal crosstalk, almost twice that of CMOS. Moreover, the vertical structure makes the heat dissipation path of CFET devices significantly different in the two transition states (inputs “1” and “0”). Based on the thermal behavior characteristics of CFET and the necessity of high-precision and rapid prediction of thermal characteristics of the devices, a thermal network model is proposed, which can quickly respond to the heat source and be extended at the array level. In the last part, we analyze the influence of load capacitance and operating frequency on the self-heating of CFET, and SHE-related reliability lifetime is predicted based on the lattice temperature obtained from the thermal network. The prediction results show that the bias temperature instability (BTI) lifetime of CFET degrades by 84% compared with standard CMOS. [ABSTRACT FROM AUTHOR]

In this letter, a new method based on the temperature dependence of gate leakage current for accurately characterizing thermal crosstalk is proposed and performed on the advanced silicon-on-insulator (SOI) MOSFETs. The developed technique enables to capture the pure thermal crosstalk effect as it excludes the self-heating impact during the measurement. Moreover, it is proven robust over a large range of gate voltages regardless of the difference of device types, which is demonstrated on a pair of devices with a shared port. The accuracy of the thermal crosstalk measurement benefits in determining the overall thermal performance of the nano-scaled circuits under the mutual heating impacts. It offers a possible hardware solution to thermal monitor and management. [ABSTRACT FROM AUTHOR]

Aggressively scaled devices with high power density wrapped around the low thermal conductivity material in narrow space are susceptible to self-heating effect, which includes serious mutual-heating due to proximity effect in multifinger/fin FETs. Obtaining local temperature instead of equivalent lumped temperature at device/circuit level quickly is crucial for designers to accurately predict front-end-of-line reliability (i.e., hot carrier injection, bias temperature instability, and time dependent dielectric breakdown) and achieve better thermal management. In this paper, we: 1) first propose an analytical model based on multistage thermal network to address effectively the self- and mutual-heating within the device; 2) validate the multistage network and proposed analytical model by COMSOL and SPICE simulation, respectively; and 3) utilize the model to investigate local temperature rise in multifinger and multifin FETs-based inverter and ring oscillator as well as provide thermal-aware IC design guideline for self-heating and reliability optimization. The results show that the analytical multistage thermal model can predict local temperature rise and quantify nonuniform temperature difference in full-frequency range, superior to the lumped thermal model. Moreover, the model can offer quick thermal analysis at the pre-Si stage for reliability prediction and thermal-aware design. [ABSTRACT FROM AUTHOR]