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In this letter, we demonstrate a high-threshold-voltage and high-current-density normally-off SiN/AlN/ GaN-on-Si MIS-HEMT with in situ low-damage H2/N2 plasma pretreatment. The in situ plasma pretreatment was performed in a plasma enhanced atomic layer deposition (PEALD) system prior to the PEALD-AlN deposition, which effectively suppress the interface trap densities between the AlN/GaN interface and increase the mobility of electrons to 198.80 cm $^{{2}}/\text {V} \cdot \text {s}$. Therefore, the devices demonstrate state-of-art characteristics with a competitive maximum drain current of 683.75 mA/mm at ${V} _{\textit {GS}} =15\text{V}$ and a high threshold of 6.28 V. The devices also show ON/OFF current ratio of $10^{{8}}$ and off-state breakdown voltage of 1778 V. [ABSTRACT FROM AUTHOR]

For devices with a 15 micron anode-to-cathode distance, nearly 1.5 times increase in the blocking (breakdown) voltage (from 692 to 1030 V) has been achieved by replacing the alloyed Ohmic contact at the anode electrode of the conventional MOS gated hybrid-anode lateral field-effect rectifier (CMLFER) with a low barrier Schottky contact. The new Schottky-MOS hybrid-anode lateral field-effect rectifier is found to offer comparable low onset voltage ( V{\textbf {ON}} of 0.68±0.13 versus 0.65±0.11 V for CMLFER) independent of the anode-to- cathode distance. The immunity of the punch through caused by drain induced barrier lowering effect is obtained through the low barrier Schottky contact in anode, which is believed to be responsible for the reduction in the leakage current, and the improvement of rectifier breakdown voltage. [ABSTRACT FROM AUTHOR]

Time-dependent OFF-state leakage behavior of AlGaN/GaN MISHEMTs on silicon substrate is investigated and a novel degradation mechanism is proposed in this paper. Under constant high voltage OFF-state stress, drain leakage current gradually increases with stress time and the behavior is gate bias and temperature-dependent. Consecutive OFF-state breakdown measurement with drain injection technique indicates that the negative shift of threshold voltage ( V\mathrm {th} ) is responsible for the increase of drain leakage current during stress measurement. It is proposed that the negative shift of V\mathrm {th} is mainly induced by the ionization of uncompensated donor like deep levels near the channel, which are most likely to be located in the 300-nm-thick unintentionally doped GaN layer above the carbon doped buffer layer. [ABSTRACT FROM PUBLISHER]

In this letter, a plasma-free etch stop structure is developed for GaN HEMT toward enhancement-mode operation. The self-terminated precision gate recess is realized by inserting a thin AlN/GaN bilayer in the AlGaN barrier layer. The gate recess is stopped automatically at the GaN insertion layer after high-temperature oxidation and wet etch, leaving a thin AlGaN barrier to maintain a quantum well channel that is normally pinched off. With addition of an Al2O3 gate dielectric, quasi normally OFF GaN MOSHEMTs have been fabricated with high threshold uniformity and low ON-resistance comparable with the normally ON devices on the same wafer. A high channel mobility of 1400 cm ^2/\textrm V\cdot \textrm s was obtained due to the preservation of the high electron mobility in the quantum-well channel under the gate. [ABSTRACT FROM AUTHOR]

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level $E1$ with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while $E2$ with an activation energy of 0.22 eV is located in the buffer layer. [ABSTRACT FROM AUTHOR]

In this paper, we report the device performance of a high-voltage normally off Al2O3/GaN MOSFET on the Si substrate. Normally off operation is obtained by multiple cycles of O2 plasma oxidation and wet oxide-removal gate recess process. The recessed normally off GaN MOSFET with 3 \mum gate-drain distance exhibits a maximum drain current of 585 mA/mm at 9 V gate bias. The threshold voltage of the MOSFET is 2.8 V with a standard derivation of 0.2 V on the sample with an area of 2 \,\times\, 2 {\rm cm}^{2} . The gate leakage current is below 10^{-6}~{\rm mA}/{\rm mm} during the whole gate swing up to 9 V and the I{\scriptstyleON}/I{\scriptstyle OFF} ratio is larger than 10^{9} , indicating the good quality of Al2O3 gate insulator. The MOSFET with 10 \mum gate-drain distance shows a three terminal OFF-state breakdown voltage (BV) of 967 V at zero gate-source bias with a drain leakage current criterion of 1 \muA/mm . The specific ON-resistance $(R_{{{\scriptstyle {\rm ON}}},{\rm SP}}) of the device is 1.6 m\Omega\,\cdot\,cm^2 and the power figure of merit (BV^2/R{{\scriptstyle ON},SP}) is 584 MW/cm^2 . [ABSTRACT FROM AUTHOR]

This letter reports a GaN high-electron mobility transistor (HEMT) with reduced current collapse using a multicycle combined plasma-free ozone oxidation and wet surface treatment before Si3N4 passivation. The surface oxide and decomposed layers could be effectively removed and a perfect AlGaN surface is obtained after the treatment. Pulsed $IV$ and RF power measurement indicate that the current collapse is greatly suppressed due to the removal of imperfect surface layer and damage free nature, providing an effective surface treatment method to improve the effect of passivation in GaN HEMT. [ABSTRACT FROM AUTHOR]

Based on our proposed self-terminating gate recess etching technique, normally-off recess-gated AlGaN/GaN MOSFET has been demonstrated with a novel method using GaN cap layer (CL) as recess mask, which, as a result, simplifies the device fabrication process and lowers the fabrication cost. The GaN CL is capable of acting as an effective recess mask for the gate recess process, which includes a thermal oxidation for 45 min at 650 °C followed by 4-min etching in potassium hydroxide (KOH) at 70 °C. After gate recess process, no obvious change is observed in terms of the surface morphology of the GaN CL, the contact resistance of the Ohmic contact formed directly on the GaN CL as well as the sheet resistance of the two-dimensional electron gas (2-DEG) channel layer under the GaN CL. The fabricated device exhibits a threshold voltage ( \(V_{\mathrm {th}})\) as high as 5 V, a maximum drain current ( \(I_{\mathrm {\rm dmax}})\) of \(\sim 200\) mA/mm, a high on/off current ratio of \(\sim 10^{10}\) together with a low forward gate leakage current of \(\sim 10^{\mathrm {-5}}\) mA/mm. Meanwhile, the OFF-state breakdown voltage ( \(V_{\mathrm {br}})\) of the device with gate-drain distance of 6 \(\mu \) m is 450 V. [ABSTRACT FROM AUTHOR]

In this letter, we investigated the behaviors of surface- and buffer-induced current collapse in AlGaN/GaN high-electron mobility transistors (HEMTs) using a soft-switched pulsed \(I-V\) measurement with different quiescent bias points. It is found that the surface- and buffer-related current collapse have different relationship with the gate and drain biases (V \(_{\mathrm { {\!GS0,}}}\) V \(_{\mathrm { {\!DS0}}}\) ) during quiescent bias stress. The surface-induced current collapse in devices without passivation monotonically increases with the negative V \(_{\mathrm { {\!GS0}}}\) , suggesting that an electron injection to the surface from gate leakage is the dominant mechanism and the Si3N4 passivation could effectively eliminate such current collapse. The buffer-induced current collapse in devices with intentionally carbon-doped buffer layer exhibits a different relationship with V \(_{\mathrm { {\!GS0}}}\) after surface passivation. The buffer-related current collapse shows a bell-shaped behavior with V \(_{\mathrm { {\!GS0}}}\) , suggesting that a hot electron trapping in the buffer is the dominant mechanism. The soft-switched pulsed \(I-V\) measurement provides an effective method to distinguish between the surface- and buffer-related current collapse in group III-nitride HEMTs. [ABSTRACT FROM AUTHOR]

This letter reports a normally-OFF Al2O3/GaN gate-recessed MOSFET using a low-damage digital recess technique featuring multiple cycles of plasma oxidation and wet oxide removal process. The wet etching process eliminates the damage induced by plasma bombardment induced in conventional inductively coupled plasma dry etching process so that good surface morphology and high interface quality could be achieved. The fully recessed Al2O3/GaN MOSFET delivers true enhancement-mode operation with a threshold voltage of +1.7~V. The maximum output current density is 528 mA/mm at a positive gate bias of 8 V. A peak field-effect mobility of 251 cm^2/V\cdots is obtained, indicating high-quality Al2O3/GaN interface. [ABSTRACT FROM AUTHOR]