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Triple heterojunction (THJ) tunneling field-effect transistors (TFETs) have been proposed to resolve the low ON-current challenge of TFETs. However, the design space for THJ-TFETs is limited by fabrication challenges with respect to device dimensions and material interfaces. This work shows that the original THJ-TFET design with 12-nm body thickness has poor performance because its subthreshold swing (SS) is 50 mV/decade and the ON-current is only 6 μA/μm. To improve the performance, the doping profile of THJ-TFET is engineered to boost the resonant tunneling efficiency. The proposed THJ-TFET design shows an SS of 40 mV/decade over four orders of drain current and an ON-current of 325 μA/μm with VGS = 0.3 V. Since THJ-TFETs have multiple quantum wells and material interfaces in the tunneling junction, quantum transport simulations in such devices are complicated. State-of-the-art mode-space quantum transport simulation, including the effect of thermalization and scattering, is employed in this work to optimize THJ-TFET design. [ABSTRACT FROM AUTHOR]

The triple heterojunction tunnel field-effect transistor (TFET) has been originally proposed to resolve the TFET’s low ON-current challenge. The carrier transport in such devices is complicated due to the presence of quantum wells and strong scattering. Hence, the full-band atomistic nonequilibrium Green’s function (NEGF) approach, including scattering, is required to model the carrier transport accurately. However, such simulations for devices with realistic dimensions are computationally unfeasible. To mitigate this issue, we have employed the empirical tight-binding mode-space approximation to simulate the triple heterojunction TFETs with the body thickness up to 12 nm. The triple heterojunction TFET design is optimized using the model to achieve a sub-60-mV/decade transfer characteristic under realistic scattering conditions. [ABSTRACT FROM AUTHOR]

Being fundamentally limited to a current–voltage steepness of 60mV/dec, MOSFETs struggle to operate below 0.6 V. Further reduction in ${V}_{\text {DD}}$ and, consequently, power consumption can be achieved with novel devices, such as tunneling transistors (TFETs) that can overcome this limitation. TFETs, however, face challenges with low ON-current leading to slow performance. TFETs made from III-nitride heterostructures are quite promising in this regard. The lattice mismatch induces a piezoelectric polarization field in a nitride heterojunction that can boost the ON-current. However, it is shown here that the carrier thermalization at the heterointerface degrades the subthreshold characteristics. Therefore, a good design should minimize the number of confined quantum well (QW) states at the heterointerface so as not to degrade the subthreshold characteristics while maintaining the lattice mismatch induced polarization to boost the ON-current. We show here that an InAlN QW on an InGaN substrate alloy engineered TFET design is promising to fulfill these requirements. Proper engineering of the alloy mole fractions and the width of the well can eliminate (or at least minimize) the undesired thermalization effects and, at the same time, provide a lattice mismatch to induce a piezoelectric field for boosting the ON-current. We have used a suitable atomistic quantum transport model to simulate these devices. The model accounts for the different mechanisms that are involved, and captures realistic scattering thermalization effects. This model has been benchmarked in our earlier work with experimental measurements of nitride tunneling heterojunction diodes and is used here to optimize the alloy engineered nitride TFET. [ABSTRACT FROM AUTHOR]

In this brief, vertical tunnel field-effect transistors (v-TFETs) based on vertically stacked heretojunctions from 2-D transition metal dichalcogenide materials are studied by atomistic quantum transport simulations. The switching mechanism of a v-TFET is found to be different from previous predictions. As a consequence of this switching mechanism, the extension region where the materials are not stacked over is found to be critical for turning off the v-TFET. This extension region makes the scaling of v-TFETs challenging. In addition, due to the presence of both positive and negative charges inside the channel, v-TFETs also exhibit negative top gate capacitance. As a result, v-TFETs have good energy-delay products and are one of the promising candidates for low-power applications. [ABSTRACT FROM AUTHOR]

Tunneling heterojunctions (THJs) have confined states close to the tunneling region, which significantly affect their transport properties. Accurate numerical modeling of THJs requires combining the nonequilibrium coherent quantum transport through the tunneling region as well as the quasi-equilibrium statistics arising from the strong scattering in the confined states. In this paper, a novel atomistic model is proposed to include both the effects: the strong scattering in the regions around THJ and the coherent tunneling. The new model matches reasonably well with experimental measurements of Nitride THJ and provides an efficient engineering tool for performance prediction and design of THJ-based devices. [ABSTRACT FROM PUBLISHER]

A high performance triple-heterojunction (3HJ) design has been previously proposed for tunneling FETs (TFETs). Compared with single HJ TFETs, the 3HJ TFETs have both shorter tunneling distance and two transmission resonances that significantly improve the ON-state current ( I\scriptscriptstyle {\text {ON}} ). Coherent quantum transport simulation predicts that I\scriptscriptstyle {\text {ON}} = 460~\mu \textsf {A}/\mu \textsf {m} can be achieved at gate length \text Lg = 15~\textsf nm , supply voltage V\textsf {DD} = 0.3~\textsf V , and OFF-state current I\scriptscriptstyle {\text {OFF}} = 1~\textsf {nA}/\mu \textsf {m} . However, strong electron–phonon and electron–electron scattering in the heavily doped leads implies that the 3HJ devices operate far from the ideal coherent limit. In this paper, such scattering effects are assessed by a newly developed multiscale transport model, which combines the ballistic nonequilibrium Green’s function method for the channel and the drift-diffusion scattering method for the leads. Simulation results show that the thermalizing scattering in the leads both degrades the 3HJ TFET’s subthreshold swing through scattering-induced leakage and reduces the turn-ON current through the access resistance. Assuming bulk scattering rates and carrier mobilities, the I\scriptscriptstyle {\text {ON}} is dropped from 460~\mu \textsf A/\mu \textsf m down to 254~\mu \textsf A/\mu \textsf m , which is still much larger than the single HJ TFET case. [ABSTRACT FROM AUTHOR]

Thickness engineered tunneling field-effect transistors (TE-TFET) as a high-performance ultra-scaled steep transistor is proposed. This device exploits a specific property of 2-D materials: layer thickness-dependent energy bandgaps ( Eg ). Unlike the conventional hetero-junction TFETs, TE-TFET uses spatially varying layer thickness to form a hetero-junction. This offers advantages by avoiding the lattice mismatch problems at the interface. Furthermore, it boosts the ON-current to $1280~\mu A/\mu m$ with 15-nm channel length. Providing higher ON currents, phosphorene TE-TFET outperforms the homojunction phosphorene and the TMD TFETs in terms of extrinsic energy-delay product. TE-TFET also scales well to 9 nm with constant field scaling E = V_{DD}/L_{ch}= 33 mV/nm. In this letter, the operation principles of TE-TFET and its performance sensitivity to the design parameters are investigated through full-band atomistic quantum transport simulations. [ABSTRACT FROM PUBLISHER]