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Abstract: This paper presents a comprehensive study on channel hot-carrier (CHC) degradation in short channel MOSFETs with high-k dielectric. Different reliability scenarios are analyzed, i.e., temperature influence, impact of high ID and dynamic operation conditions. To explain the CHC damage behavior in short channel devices, we divide the total CHC degradation in two components: the classical CHC damage located at drain side and the degradation produced by the voltage drop over the gate dielectric, which can be considered as bias temperature instability (BTI). [Copyright &y& Elsevier]

Abstract: A comparison between the Channel Hot-Carrier (CHC) degradation on strained pMOSFETs with SiGe source/drain (S/D) based on different gate dielectric materials, as SiON or HfSiON, has been done. The influence of the device channel orientation, channel length and temperature on the CHC damage has been studied. [Copyright &y& Elsevier]

The channel hot-carrier (CHC) degradation in metal-oxide semiconductor field-effect transistors based on a high-k dielectric with strained-Si/relaxed Si1-xGex structures has been little studied so far. However, due to the high mobility enhancement observed in these samples, a deeper study of the CHC impact on them is necessary. In this article, the effects of the Ge content, overgrowth, channel length, and operating temperature on the CHC degradation have been analyzed. The results show that devices with higher mobility suffer larger CHC aging both at room temperature and in the elevated temperature range. [ABSTRACT FROM AUTHOR]

Abstract: Hot-carrier degradation in pMOS transistors with Si1– x Ge x implantations in the source and drain areas is analyzed (SiGe S/D). A simulation methodology is developed to translate the effects to circuit simulators. This methodology is applied to study hot-carrier degradation in CMOS inverters designed with SiGe S/D pMOS transistors. The results show that although pMOS transistors with embedded SiGe S/D have a better device performance, these devices are more sensitive to hot-carrier degradation at both the device and circuit levels. [Copyright &y& Elsevier]

Abstract: A comparison between pMOS and nMOS short channel transistors with high-k dielectric subjected to channel hot-carrier (CHC) stress is presented. Smaller CHC degradation is observed in pMOS devices. At high temperature, the CHC degradation increases for pMOS and nMOS. The temperature dependence of the CHC degradation has been explained, for both transistor types, by considering a larger influence of a bias temperature instability (BTI)-related component of the total CHC induced degradation. [Copyright &y& Elsevier]

Abstract: The channel hot-carrier (CHC) degradation in nMOS transistors with high-k dielectric subjected to different AC stress configurations was studied. The influence of the gate AC stress waveform parameters on the CHC degradation was analysed, when a constant drain voltage was applied. For short channel devices, CHC degradation has been found to be dependent on duty-cycle and rise/fall times and independent of frequency. These results have been observed independently of the gate dielectric material (SiO2 or high-k). Moreover, the CHC damage in a nMOS transistor subjected to stress conditions which simulate its operation within a CMOS inverter has been also analysed. Lower degradation is observed in this case. [Copyright &y& Elsevier]