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This paper presents a one‐sided 10‐transistors static‐random access memory (SRAM) cell appropriate for the internet of things (IoT) applications in which energy‐efficient SRAM cells are necessary to raise the battery lifetime. The bit‐cell core of the proposed SRAM cell is composed of two inverters with different structures based on the gate‐wrap‐around (GWA) carbon nanotube (CNT)‐gate‐diffusion input (GDI) technique and only one‐bit line to perform both read and write operations to minimize active power consumption. The proposed bit‐cell uses a transmission gate network and write‐assist schemes to significantly improve the write‐ability and stack read‐decoupling technique to enhance hold‐/read‐stability. Moreover, a memory mini‐array has been implemented using the proposed cell along with all the principal circuitries. Extensive Monte Carlo (MC) simulations show that write/hold/read static noise margins (SNMs) are improved by about 1.252, 1.196, and 1.152 times, respectively. Also, the results of evaluating the write‐ and read‐yield parameters for the proposed SRAM bit‐cell are about 22% and 13% better than counterpart bit‐cell designs, respectively. In addition, the bit error rate (BER) and energy dissipation parameters for the proposed memory cell are almost 61% and seven times higher than the studied SRAM bit‐cell in the same simulation process. Finally, to evaluate the effectiveness of the proposed SRAM bit‐cell in the real‐world application, a memory array architecture with an online (or off‐chip) adaptive power supply voltage based on a hardware algorithm for storing digital images at a minimum energy dissipation is proposed. Our simulation results emphasize that the proposed memory array can be a good candidate for energy‐efficient and noise‐immunity IoT platforms. [ABSTRACT FROM AUTHOR]

In this work, unique characteristics of carbon nano-tube field effect transistor (CNTFET) are used to propose a universal cell with a simple architecture based on the binary modified gate-diffusion input (m-GDI) method for designing fundamental gates in the voltage-mode multiple-valued logic (MVL) with any arbitrary number of logic levels for processing at nano-scales. The results of the simulations confirm more energy-efficiency, larger noise margins and lower sensitivity of the proposed designs in different logic levels as compared with the state-of-the-art designs. The effects of the process, voltage and temperature (PVT) variations are extensively evaluated by Monte–Carlo simulation. According to the results, the proposed designs are robust against PVT variations and noise. The proposed structure is applied to the MVL-based image processing. The results show that the output images of the proposed MVL-based inexact gates have an appropriate quality in compare with the images generated by the other similar exact gates. [ABSTRACT FROM AUTHOR]

Reversible or information lossless gates have applications in nano-technology, digital signal processing (DSP), communication, computer graphics and cryptography. Gate-diffusion input (GDI) technique can provide the possibility of designing fundamental gates in ultra-low power and layout chip area with low number of transistors. A reversible logic-based single-bit magnitude comparator (RMC) circuit is presented by using the modified-GDI (m-GDI) method-based reversible gates for designing RMC in any arbitrary number of bit levels for processing at nano-scales. In this paper, several figure of merits (FOMs) like: energy consumption-propagation delay product (EDP) and worst delay-power consumption-chip area product (DPA) are evaluated and compared with other designs. The simulation results show the improvement of the evaluation parameters of the proposed RMC in compare with the other similar basic GDI-based comparators. Also, according to the simulation results, presented comparator is capable to work at extensive frequency ranges with higher maximum operating frequency (f max.). The effects of different process, voltage and the temperature (PVT) variations are extensively evaluated by Monte-Carlo simulation. According to the results, the proposed circuit is robust against PVT variations and also noise-tolerable parameter. Moreover, the proposed RMC architecture is used in images applications. The results show that output images of the proposed inexact RMC have a very high quality and resemblance to the images generated by exact RMC, thus excellent values for the peak signal-to-noise ratio (PSNR) and mean structural similarity index metric (MSSIM) indicate that the proposed inexact RMC circuit has a proper accuracy for applications such as: comparative analysis in medical images, motion detector, edge detection and segmentation in nano-technology. Therefore, using the proposed scheme can be improved in comparator circuit in chips for future generation of VLSI and ULSI blocks, like: nano-processors performance. [ABSTRACT FROM AUTHOR]