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A new 1‐bit full adder (FA) cell illustrating low‐power, high‐speed, and a small area is presented by a combination of transmission gate (TG), pass transistor logic (PTL), and float techniques. Using the proposed cell, a 4:2 compressor is implemented and its performance is investigated under diverse circumstances of voltage, temperature, and driving. The process and corners are evaluated through the process‐voltage‐temperature (PVT) variations and the Monte Carlo method (MCM), respectively. The accuracy and reliability of the proposed 4:2 compressor are confirmed carefully. Utilising the proposed FA and the compressor, an efficient 8‐bit subtractor is implemented for bioimage processing, in particular for difference detection of images. A new mechanism is presented to improve the detection performance of digital signal processors (DSPs) by the addition and subtraction of two images for their difference. The quality of the resulted image confirms the efficiency of the proposed circuits and the method. The high performance of the circuits makes them a promising candidate for the next generation of integrated circuits (ICs) applicable to medical image processing. [ABSTRACT FROM AUTHOR]

• Using the carbon nanotube field-effect transistors technology to design approximate arithmetic circuits. • The gate diffusion input and dynamic threshold techniques are integrated to attain efficient circuits. • The presented approximate full adders show reliable performance during image processing. • The approximate full adders applied in bioimage processing. • Fat and water can be detected in bioimages by the presented approximate cells. Two new approximate full adders (FAs) are proposed by the multiplexers (MUXs) and OR gates with the gate diffusion input (GDI) technique. The cells are named GDI-based MUX approximate FAs (GMAFAs), GMAFA1, and GMAFA2. The threshold voltage drop of the GDI-based circuits is solved by carbon nanotube field-effect transistors (CNTFETs) technology and the dynamic threshold (DT) technique. The FAs have accurate C out , approximate Sum, and a low number of transistors. They are low-power, high-speed, and energy-efficient for ripple-carry adders (RCAs). The GMAFA1 and GMAFA2 have a total area of 0.068 µm2 and 0.119 µm2, respectively, which demonstrate 27.8% and 54.55% improvement in power-delay-area-product (PDAP) in comparison with the best references. The results of error distance (ED), normalized mean error distance (NMED), power signal-to-noise ratio (PSNR), and energy-saving confirm the accuracy of the presented cells for image processing applications. [Display omitted] [ABSTRACT FROM AUTHOR]

Integrated circuits (ICs) employ static and dynamic logic to improve performance and scalability. This paper presents a new circuit design approach named pseudo-dynamic logic (PDL), which shows the advantages of both static and dynamic cells. The PDL is evaluated by using a new full adder cell with 18 transistors. In the presented full adder, gate diffusion input (GDI), transmission gate (TG), and float techniques are combined, and pull-up or pull-down networks are changed into a new configuration so that the number of transistors and internal nodes will decrease. Post-layout simulations and digital image addition are performed to evaluate the real environment and practical application of the cell. Peak signal to noise ratio (PSNR), mean square error (MSE), and structural similarity index metric (SSIM) are calculated to study the cell performance in image processing. Compared to the dynamic and static circuits, the proposed PDL-based full adder cell performs better, and the results validate its effectiveness. [ABSTRACT FROM AUTHOR]

Different digital multipliers have resulted from various algorithms and hardware designs. This article presents a high-performance multiplier by a novel AND gate and a modified hybrid full adder (FA) cell. The AND is designed by using the pass transistor logic (PTL) technique and a speed-up transistor, while the FA is based on the transmission gate (TG). Low-power, high-speed, low power-delay-product (PDP), and high competency of both circuits for using in sophisticated structures like multipliers are confirmed by mathematical relations. The proposed 4-bit array multiplier circuit along with the pad has a 2.87 mm2 total area and is investigated under different circumstances including V DD , frequency, load capacitances, and process-voltage-temperature (PVT) variations using Monte Carlo method (MCM) by HSPICE tool and 90 nm technology. The efficiency of the multiplier in image processing applications is proved with average improvements of 12.61% and 32.045% for peak signal-to-noise ratio (PSNR) and PDP compared to state-of-the-art designs, respectively. The overall results of the multiplier approve its capability for digital signal processors (DSPs). [ABSTRACT FROM AUTHOR]