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A wireless vision sensor network (WVSN) is built by using multiple image sensors connected wirelessly to a central server node performing video analysis, ultimately automating different tasks such as video surveillance. In such applications, a large deployment of sensors in the same way as Internet-of-Things (IoT) devices is required, leading to extreme requirements in terms of sensor cost, communication bandwidth and power consumption. To achieve the best possible trade-off, we propose in this paper a new concept that attempts to achieve image compression and early image recognition leading to lower bandwidth and smart image processing integrated at the sensing node. A WVSN implementation is proposed to save power consumption and bandwidth utilization by processing only part of the acquired image at the sensor node. A convolutional neural network is deployed at the central server node for the purpose of progressive image recognition. The proposed implementation is capable of achieving an average recognition accuracy of 88% with an average confidence probability of 83% for five subimages, while minimizing the overall power consumption at the sensor node as well as the bandwidth utilization between the sensor node and the central server node by 43% and 86%, respectively, compared to the traditional sensor node. [ABSTRACT FROM AUTHOR]

This article presents a low-power multi-mode CMOS vision sensor with mixed-signal in-sensor computation capabilities targeting the next-generation wireless sensing applications. To support the always-on and scene-adaptive edge computing scenarios with low power and low bandwidth, the sensor is reconfigurable for three operation modes, namely: 1) motion sensing (MS); 2) object segmentation (OS); and 3) full imaging (FIM). A mixed-signal cooperative scheme of frame differencing (FD) and background subtraction (BS) is proposed to achieve high-accuracy MS with varying object sizes and speeds. The mixed-signal BS-based OS can minimize both object localizing and imaging efforts for object analysis upon motion triggering, while FIM enables complete scene recording for the identified object of interest. The complete CMOS vision sensor is implemented through reconfigurable and fully dynamic mixed-signal processing at both pixel and column levels cooperatively to achieve low power and compact area. Fabricated in a 0.18- ${ {\mu }}\text{m}$ CMOS, the 256 $ {\times }$ 216 chip prototype achieves the cooperative MS with only 2.36 ${\mu }\text{W}$ at 15 frames/s, when composed of 14 FD frames (147 nJ/frame) and 1 BS frame (302 nJ/frame). The OS mode consumes 1.44~2.04 $ {\mu }\text{J}$ /frame at 0%~100% object occupancy, linearly corresponding to 41%~16% power saving when compared with the conventional digital OS. The FIM mode operates with only 1.41 ${\mu }\text{J}$ /frame for complete scene recording. The achieved energy efficiencies for all operation modes compare favorably with the state of the art. [ABSTRACT FROM AUTHOR]

This brief presents a low-power compression-based CMOS image sensor for wireless vision applications. The sensor implements low-bit-depth imaging with planned sensor distortion (PSD) to effectively compress both data bandwidth and processing power while maintaining high reconstruction image quality. Accordingly, a column-parallel microshift-guided successive-approximation-register (SAR) ADC is proposed to enable 3-bit PSD imaging based on a ${3\times 3}$ pattern. To support normal imaging with low area overhead, the circuit is reconfigurable as an 8-bit SAR/single-slope ADC. The data bandwidth is further compressed by a customized lossless encoder based on predictive coding and run length coding. A ${256\times 216}$ prototype imaging system composed of the compression-based image sensor and the lossless encoder is fabricated in a 0.18- ${\mu }\text{m}$ standard CMOS process. Measurement results show that the image sensor achieves 3 bit/pixel (bpp) with 34.9-dB reconstruction peak signal-to-noise ratio (PSNR) and 0.91 structural similarity index (SSIM). With 1/4 spatial downsampling and lossless encoding, 0.31 bpp is obtained with 29.2-dB PSNR and 0.83 SSIM. The sensor consumes $14.8~{\mu }\text{W}$ (full resolution) and $4.3~{\mu }\text{W}$ (downsampling) at 15 fps, achieving state-of-the-art FoMs of 17.8 and 5.2 pJ/pixel $\cdot $ frame, respectively. Including the encoder, the overall system dissipates as low as $1.2~{\mu }\text{J}$ /frame, making it an attractive solution for wireless sensor networks. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel interpolation technique for the division of focal plane polarization image sensors, which adaptively determines the polarization residuals of a pixel in four directions. We have analyzed the performance of different micro-polarizer patterns by interpolation and optimized for a polarization microscope with maximized interpolation accuracy. Specifically, we applied our proposed algorithm on patterns of four micro-polarizers (oriented along 90°, 135°, 45°, and 0°), three micro-polarizers (oriented along 0°, 45°, and 90°), and two micro-polarizers (oriented along 0° and 45°), respectively. The experimental results reveal that the three-micro-polarizer pattern outperforms the other micro-polarizer patterns for recovering the missing polarization information in terms of mean square error (MSE). Moreover, the visual comparison is enabled with the fibrous structure of human liver carcinoma tissues, which shows excellent agreement with the reported MSE comparison. [ABSTRACT FROM AUTHOR]

In this paper, we present a block-matching and 3-D filtering (BM3D) algorithm dedicated to the division-of-focal-plane (DoFP) polarization images. This algorithm based on a non-local collaborative filtering method is capable of exploiting all the different polarization channels simultaneously. Compared with the previously reported implementations for DoFP sensors, the proposed algorithm attenuates Gaussian noise in the transform domain by stacking similar 2-D image patches to form a 3-D block. According to our extensive experimental results, the proposed algorithm outperforms all the existing denoising algorithms for DoFP images including the state-of-the-art principle component analysis in terms of peak-signal-to-noise-ratio and structural similarity index. Moreover, the comparison is further extended to visual comparison, it is indicated that the image details are well-preserved by the proposed BM3D algorithm. [ABSTRACT FROM AUTHOR]

In this paper, we present a novel K times singular value decomposition (K-SVD) based denoising algorithm dedicated to the division-of-focal-plane (DoFP) polarization image sensors. The proposed method is based on sparse representation over trained dictionary. Using the proposed K-SVD algorithm to update the dictionary, the image content can be more effectively expressed. Compared with the previous denoising algorithms, the proposed implementation is capable of decomposing the input DoFP image as the optimum sparse combination of the dictionary elements, which are generated by orthogonal matching pursuit. This not only separates the Gaussian noise from the target DoFP image with a significantly elevated peak signal-to-noise ratio (PSNR) but also well-preserves ythe details of the original image. According to our extensive experimental results on various test images, the proposed algorithm outperforms the state-of-the-art principal component analysis based denoising algorithm by 3 dB in terms of PSNR. Moreover, visual comparison results, which show excellent agreement with the PSNR results, are presented as well. [ABSTRACT FROM AUTHOR]

Laser Doppler imaging (LDI) measures particle flows such as blood perfusion by sensing their Doppler shift. This paper is the first of its kind in analyzing the effect of circuit noise on LDI precision which is distinctively different from conventional imaging. Based on this result, it presents a non-correlated-double-sampling (non-CDS) pixel readout scheme along with a high-resolution successive-approximation-register (SAR) analog-to-digital-converter (ADC) with 13.6b effective resolution (ER). Measurement results from the prototype chip in 0.18 \mum technology confirm the theoretical analysis and show that the two techniques improve LDI sensing precision by 6.9 dB and 4.4 dB (compared to a 10b ADC) respectively without analog pre-amplification. The sensor's ADC occupies 518\ \mum\times 84\ \mum and is suitable for fast column parallel readout. Its differential non-linearity (DNL), integral non-linearity (INL), and input referred noise are +3.0/-2.8 LSB, +24/-17 LSB, and 110 \muVrms respectively, leading to a Figure-of-Merit (FoM) of 23 fJ/state which makes it one of the most energy efficient image sensor ADCs and an order of magnitude better than the best reported LDI system using commercial high-speed image sensors. [ABSTRACT FROM PUBLISHER]

This paper presents a low-power column-parallel inverter-based cyclic analog-to-digital converter (ADC) for CMOS image sensor readout circuit. By partially floating the capacitors inside the multiply digital-analog-converter during the least significant bit (LSB) quantization, the amplifier load capacitance could be significantly scaled down, which allows much higher settling speed and shorter cycle period. Since the signal-to-noise ratio for LSB cycle is relaxed due to the residual amplification, the proposed capacitance scaling only contributes ignorable input-referred quantization noise. Using the proposed techniques, a cyclic ADC can operate under 50% power consumption without suffering conversion rate, noise performance, and linearity. A 12-b quantization resolution test chip is fabricated using the TSMC 0.18- \mu \textm technology with 110 column-parallel ADC channels and 10.08- \mu \textm \times 750 - \mu \textm column pitch. The 3.5/−2 LSBs integral nonlinearity and 10.1-b effective-number-of-bit are measured under 2- \mu \texts sampling rate with 120- \mu \textW power consumption per channel. [ABSTRACT FROM AUTHOR]

This paper presents a low-power megapixel image sensor design. In this paper, a column-parallel 11-bit two-step quantization scheme is proposed. It consists of a 3-bit single-slope analog-to-digital converter (ADC) and an 8-bit successive approximation register (SAR) ADC. The power consumption of the column-parallel circuitry is significantly reduced when compared with the traditional single-slope ADC and other low-power ADC schemes because smaller SAR ADC reference voltages are selected after quantizing the first three most significant bits. In addition, as only an 8-bit SAR ADC is required in the proposed quantization scheme, the capacitor array matching can be greatly relaxed compared with an 11-bit SAR ADC thus, resulting in noncalibration feature. A 1200\,\times\,800 pixel resolution color CMOS image sensor (CIS) is fabricated using TSMC 0.18-\mum CIS technology. The measurement result shows that the total power consumption figure-of-merit of this research is only 1.33 mW/megapixel/frame under 3.3-V (analog)/1.8-V (digital) power supply. [ABSTRACT FROM AUTHOR]

The concept of compressive acquisition image sensor is to compress data while sensing and prior to storage. In this paper, the concept of compressive acquisition image sensor is developed, implemented and experimentally validated for both spatial and temporal domains. In the proposed scheme, the image sensor array is divided into quadrants integrating logic circuitry which performs online spatial compression of the raw data prior to storage. The quadrants are subsequently further classified into background/non-background quadrants by an off-array judge logic which enables to adaptively track the associated temporal information. Temporal redundancy between frames is hence removed in the readout phase. The proposed compressive acquisition algorithm is simulated and experimentally validated for both spatial and temporal domains through a hardware prototype. Experimental results show that the proposed algorithm enables more than 50% memory saving at a PSNR level of 26 dB with around 0.5 BPP. This result not only greatly reduces the memory requirements for a digital pixel CMOS image sensor, but also results in area saving as data is only stored after being compressed. [ABSTRACT FROM AUTHOR]

In this paper, we present a 4T low-power linear-output current-mediated CMOS APS imager, in which reset and read-out operations are carried-out simultaneously on two pixels of the same row. The proposed operating technique greatly simplifies the pixel architecture with only four transistors and two control signals required, while six transistors and four control lines are required by its current-mediated counterpart. The imager achieves fixed pattern noise (FPN) correction during pixel-readout and exhibits a power consumption which is independent of the imager array size, since only a single current source is solicited at any given time due to the array-level operating technique. A linearization circuit technique using the transistor's channel length modulation effect is employed enabling to double the linear range of the pixel's photon-to-output signal transfer function. Performance analysis and experimental results are presented for a 32\,\times\,32 image sensor array prototype, fabricated using AMS 0.35-\mum process. The pixel size is 6.5\,\times\,6.5 \mu\ m^2 with 22% fill-factor. The chip total power consumption is less than 1 mW, at 50 frames/s with a 3.3 V power supply. [ABSTRACT FROM AUTHOR]