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Soft-input soft-output (SISO) detector for the iterative detection and decoding of coded spatial modulation (SM) signals needs to compute the extrinsic bit log-likelihood ratio (LLR) associated with each detected bit. The maximum logarithmic maximum a posteriori (max-log-MAP) detector is known to perform closely to the optimal logarithmic maximum a posteriori (log-MAP) detector with much lower computational complexity. In this paper, we first apply several mathematical tricks to derive a new and low-complexity algorithm for the max-log-MAP detector. The proposed algorithm features a new tree pruning technique to visit few lattice points and a smart list administration technique to retain a max-log-MAP detector. By following the proposed algorithm, we then design a hardware architecture for SISO detection of coded SM signals over the scenario of 64-QAM symbols, 8 transmit antennas, and 4 receive antennas. Under the TSMC 40 nm CMOS technology, the VLSI implementation results reveal that our architecture requires 46.4K gates and leads to detection throughput 450 Mbps, while operating at clock frequency 400 MHz and consuming power 46 mW. Being the first hardware architecture for SISO detection of coded SM signals, our proposed low-cost max-log-MAP detector is very attractive. [ABSTRACT FROM AUTHOR]

In the generalized spatial modulation (GenSM) multiple input multiple output (MIMO) system, each block of data bits is mapped to a set of spatially multiplexed (SMX) symbols and an index of transmit antenna combination (TAC) of active antennas. The difficulty for the GenSM MIMO receiver is to detect the SMX symbols and TAC index simultaneously. Recently, we applied the conventional sphere decoding algorithm (SDA) successively to achieve the exact maximum likelihood detection (MLD) of GenSM MIMO signals. The SDA scheme suffers from variable computational complexity and leads to hardware detectors with variable throughput rate. Instead, fixed-complexity tree search algorithms, e.g., reduced fixed sphere decoding (rFSD), with nearly MLD performance are employed to facilitate hardware implementation. Here, we propose to apply the rFSD successively and design a hardware architecture for detecting GenSM MIMO signals under the scenario of 5 transmit antennas, 2 transmit radio frequency chains, 4 receive antennas, and 64-QAM SMX symbols. The VLSI implementation results under the TSMC 90nm CMOS technology reveal that our architecture requires 276.7K gates and provides detection throughput 1.613 Gbps, while operating at 322.6 MHz. Compared with other related architectures, our architecture provides higher detection throughput rate and is of better hardware efficiency. [ABSTRACT FROM AUTHOR]