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A novel beta-quasi-Z-source (β-qZS) converter is proposed for an isolated dc–dc converter with the buck (step-down) and boost (step-up) functions. The β-qZS isolated dc–dc converter addresses the common challenges such as components stresses, reliability, suppression of switch voltage overshoot, size, and power derating in the existing impedance source-based isolated dc–dc converter applications. In addition, the proposed topology dealt with operating duty cycle constraint and loss of duty cycle phenomenon in the Z/qZS galvanically isolated dc–dc converters. This article describes the configuration and provides the principle of operation for the proposed β-qZS converter topology. A laboratory prototype is developed, and the experimental results satisfy the theoretical analysis. [ABSTRACT FROM AUTHOR]

In this article, two configurations of the quadratic quasi-Z-source (Q-qZS) isolated dc–dc converters are presented, namely continuous input current and discontinuous input current configurations. The operating principles and steady state of the continuous input current topology analyzed in this article is characterized with the following features: 1) wider operating range due to buck and boost functions in a single stage; 2) draws continuous input current; 3) low input current ripple compared with other qZS-based isolated dc–dc converters; 4) better reliability and good immunity against EMI noise; 5) common ground between the input source and the inverting bridge; and 6) continuous control over the entire operating range. Compared with other qZS-based isolated dc–dc converters, lower current stresses on active and passive components used are realized. Hence, the total magnetic volume/energy required by the proposed converter is reduced with the potential of achieving high power density. A prototype of 40–140 V input voltage, 300 V output, and 550 W rated power is developed to validate the performance of the proposed converter presented. [ABSTRACT FROM AUTHOR]

This letter proposes a modified double-dual-boost (DDB) high-conversion-ratio dc–dc converter. The proposed converter is derived from the existing DDB converter by a simple yet effective circuit modification and inherits all the advantages of the existing DDB converter. In addition, the input and output can share a common ground due to the circuit modification, enabling the use of low-side gate drivers for all switching devices. When compared with the existing DDB converter, the proposed converter requires only one more capacitor, and the seemingly two inductors can be integrated into a single inductor. Thus, the overall magnetic volume is the same as the conventional converter. To validate the performance of the proposed converter, a 2-kW prototype was fabricated and tested. [ABSTRACT FROM AUTHOR]

In this letter, an asymmetrical pulsewidth modulation (PWM) scheme is proposed to solve the output voltage unbalance and voltage gain issues of the input-parallel output-series (IPOS) converter when $D < 0.5$. With the proposed scheme, the natural output voltages balancing and high step-up conversion ratio can be extended when $D < 0.5$. As a result, combined with the conventional PWM scheme, the duty cycle limitation of the IPOS converter is completely eliminated without any extra components or dedicated control. A 2-kW prototype of the IPOS converter was built and tested to verify the performance of the proposed PWM scheme. [ABSTRACT FROM AUTHOR]

This article presents current-fed (CF) full-bridge (FB) isolated dc–dc converter using quasi-Z-source network. Owing to its inherent buck–boost and clamping function, the proposed converter can effectively eliminate start-up and switch voltage overshoot problems. In addition, when compared with the conventional CF-FB converter with active clamp, switch current stress is much reduced and less active switches are required. Operation principles of the proposed converter are analyzed in detail. The simulation and experimental results with 1-kW prototype are also provided to verify theoretical analysis. [ABSTRACT FROM AUTHOR]

This article presents a novel two-channel light emitting diode (LED) current balancing method using current-fed (CF) quasi-Z-source (qZS) dc–dc converter. The proposed LED driver is simple in structure and requires minimal number of component counts. Currents flowing through the two LED strings are automatically balanced owing to charge (amp–sec) balance condition on capacitors in the CF–qZS network. Since current balancing is achieved automatically by passive components, current control of the proposed converter is very simple. In addition, the proposed circuit uses only one active switch and one diode. The operating principle and characteristics of the proposed two-channel LED driver are analyzed in detail. To verify validity of the proposed converter, 80 W prototype is built and tested. [ABSTRACT FROM AUTHOR]

In this letter, an asymmetrical pulsewidth modulated (PWM) scheme is proposed to solve the inductor current unbalance and nonlinear voltage gain issues of the series-capacitor (SC) high-conversion-ratio (HCR) converter when D > 0.5. With the proposed scheme, the converter can achieve both current balancing and high step-down conversion even for D > 0.5. As a result, combined with the conventional PWM scheme, the duty cycle limitation of the SC-HCR converter is completely eliminated. A 2-kW prototype SC-HCR converter was fabricated and tested to validate the performance of the proposed PWM scheme. [ABSTRACT FROM AUTHOR]

In this paper, a new nonisolated high-voltage-gain boost converter is proposed. The proposed converter is constructed by adding an additional inductor to a conventional three-level-boost (TLB) converter. When compared with the conventional boost and TLB converters, the proposed converter can achieve higher voltage conversion ratio with reduced voltage and current stresses in the switches. In particular, the proposed converter can reduce the losses of active devices by reducing the current of the switch compared to conventional converters, thus, can achieve high efficiency. In addition, the proposed converter automatically balances the output voltages for an unbalanced load without the need for any additional control strategy or auxiliary circuit. A 2-kW prototype converter was built and tested to verify performances of the proposed converter. [ABSTRACT FROM PUBLISHER]

In this letter, a modified series-capacitor (SC) high conversion ratio (HCR) dc–dc converter is proposed. The proposed converter inherits most of the advantages of the existing SC HCR dc–dc converter and can eliminate the problem of high switch-voltage stress of the existing converter encountered during start-up using a simple circuit modification. Although an extra capacitor is required in the proposed converter, total series capacitance of the proposed converter is the same as that of the conventional SC converter. In addition, input capacitance of the proposed converter can be reduced by less than half of that of the SC buck converter. A 1-kW prototype converter is built and tested to verify the performance of the proposed converter. [ABSTRACT FROM PUBLISHER]

Z-source inverters have become a research hotspot because of their single-stage buck–boost inversion ability, and better immunity to EMI noises. However, their boost gains are limited, because of higher component-voltage stresses and poor output power quality, which results from the tradeoff between the shoot-through interval and the modulation index. To overcome these drawbacks, a new high-voltage boost impedance-source inverter called a switched-coupled-inductor quasi-Z-source inverter (SCL-qZSI) is proposed, which integrates a switched-capacitor and a three-winding switched-coupled inductor (SCL) into a conventional qZSI. The proposed SCL-qZSI adds only one capacitor and two diodes to a classical qZSI, and even with a turns ratio of 1, it has a stronger voltage boost-inversion ability than existing high-voltage boost (q)ZSI topologies. Therefore, compared with other (q)ZSIs for the same input and output voltages, the proposed SCL-qZSI utilizes higher modulation index with lower component-voltage stresses, has better spectral performance, and has a lower input inductor current ripple and flux density swing or, alternately, it can reduce the number of turns or size of the input inductor. The size of the coupled inductor and the total number of turns required for three windings are comparable to those of a single inductor in (q)ZSIs. To validate its advantages, analytical, simulation, and experimental results are also presented. [ABSTRACT FROM AUTHOR]

The traditional neutral point clamped (NPC) inverter has short-circuit problem. The risk of short-circuit can be decreased by using dead-time in the switching signals. However, the dead-time decreases the achievable output voltage and causes distortion in the waveforms. To overcome the short-circuit problem, dual-buck NPC (DB-NPC) and split-inductor NPC (SI-NPC) inverters have been researched. However, the voltage stress of the two external diodes in the DB-NPC inverter is higher. On the other hand, the SI-NPC inverter has a problem of generating huge voltage spikes in the dead-time, which can destroy the semiconductor devices. In addition, the SI-NPC inverter cannot provide reactive power. This article presents a family of NPC inverters consisting of single-phase, three-phase, and cascaded inverters. The proposed inverters have no short-circuit and dead-time issues, therefore no high voltage and current spikes are caused. Also, the dead-time in the switching signals can be minimized. As a result, the magnitude of the output waveforms can be increased, and quality can be improved. Unlike the DB-NPC inverter, the voltage stress of all the semiconductor in the proposed inverter is lower, and unlike the SI-NPC inverter the proposed inverter provides reactive power. In this article, the proposed three-level NPC inverter is analyzed, designed, and tested. The voltage stress of the semiconductor devices in the proposed inverter is half of the source voltage, whereas in the conventional DB-NPC inverter the voltage stress of the two external diodes is the source voltage. In addition to the aforementioned benefits, the proposed cascaded inverter reduces the total number of inductors. To verify the analysis, detailed simulation, and experimental results of the proposed three-level inverter with input voltage 640 V, output power 1.2 kW, and output voltage 220 Vrms are provided. [ABSTRACT FROM AUTHOR]

In this paper, two single-phase single-stage split-inductor buck–boost inverters are proposed: type-I and II. The proposed type-I is unity power factor inverter, while the proposed type-II inverter is suitable for any power factor. Both topologies remove the shoot-through problem. Furthermore, the reverse recovery issues for all switches are eliminated; therefore, mosfets are used to obtain higher efficiencies. The proposed inverters operated at higher switching frequencies confer the additional benefit of smaller passive components. The current stresses of the two switches in the proposed type-I and II inverters are lower of the conventional boost inverter. The dead time can be eliminated at both the high and line switching frequencies. In addition, the inductor conduction loss is minimized to improve efficiency. Moreover, the voltage stresses of the two switches in the type-I inverter can be much lower of its counterpart boost inverter. Most importantly, unlike the conventional high-reliability inverters, the magnetic volume of the proposed high-reliability type-I and II inverters is same of its counterpart boost inverter. The experimental results obtained for 500 W, 110 Vrms, 60 Hz hardware prototypes verify the analysis. [ABSTRACT FROM AUTHOR]