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This paper proposes a control for a single-phase grid-tied inverter operating in both continuous current mode (CCM) and discontinuous current mode (DCM) to minimize inductors without worsening a current total harmonic distortion (THD). In a conventional CCM/DCM control, an inductance is required in a DCM nonlinearity compensation; consequently, the control becomes inductance-dependent. In the proposed control, a duty ratio at a previous calculation period is utilized to compensate for the DCM nonlinearity and detect current modes independently from the inductance. A 4-kW 100-kHz prototype of the inverter with two designs of the inductor is realized to confirm the effectiveness of the proposed control. When the inductor impedance, which is normalized by an inverter impedance, is reduced from 1.8% to 0.5%, volume and material cost of the inductor are reduced by 51% and 62%, respectively, whereas the loss at a light load of 0.1 p.u. is reduced by 35%. However, due to this inductor minimization, the current THD at a rated load increases from 2.3% to 8.7% with the conventional control, violating the grid current harmonic constraint regulated by standard IEEE-1547. The proposed CCM/DCM control reduces the current THD from 8.7% to 2.1%, enabling the inductor minimization and satisfies the grid standard. [ABSTRACT FROM AUTHOR]

This paper presents a high power density design for a step-down rectifier incorporating a modular multilevel converter (MMC) in a power system connected to a 6.6 kV ac grid. In particular, the relationship among the number of cells, the output voltage of the MMC, and the overall volume is clarified. A proposed design flowchart focuses on minimizing volumes of cell capacitors, heat sinks, and arm inductors by using optimal number of cells. Moreover, the commercial electrolytic capacitors are used as the cell capacitor. Besides, the formulae used to determine the ripple currents in the electrolytic capacitor and the arm inductor are presented, along with that for the semiconductor loss. Each of these formulae were verified experimentally using a miniature model and theoretical values from all formulae agree with the measured values within minimal deviations that are discussed with regard to the design of a practical converter for a 6.6 kV system. Finally, the conditions necessary to achieve high power density in an MMC are provided, based on volume evaluations of the electrolytic capacitor, the arm inductor, and the heat sink. Using this optimization process, an MMC design achieved a volume reduction of approximately 90% compared to a conventional system. [ABSTRACT FROM PUBLISHER]

This paper proposes a hybrid current mode between triangular current mode (TCM) and discontinuous current mode (DCM) in order to improve a wide-load-range efficiency for a high-frequency SiC-based boost converter. At rated load, TCM, where the zero-voltage switching (ZVS) is achieved, is used in order to increase the switching frequency and minimize the boost converter. At light load, the hybrid discontinuous current mode (HDCM), where the TCM current is flown during the zero-current interval of DCM, is applied in order to achieve both ZVS and a reduction of a current ripple. This maintains a high efficiency over a wide load range. A 1-kW prototype is realized to compare HDCM over continuous current mode (CCM), DCM, and TCM. Compared to TCM, the root-mean-square current is reduced up to 56.6% with HDCM. Consequently, the efficiency of HDCM at light load of 0.1 p.u. is improved by 3.1%. Compared to DCM, the average-current ripple in HDCM is reduced by 82.3%, whereas the efficiency of HDCM at light load of 0.1 p.u. is improved by 1.5%. Finally, when the current ripple of CCM is designed to be half of TCM, the efficiency of HDCM at rated load is improved by 0.9% compared to CCM. [ABSTRACT FROM AUTHOR]

This paper discusses a new circuit configuration and a new control method for a single-phase ac–dc converter with power factor (P.F.) correction and a power pulsation decoupling function. The proposed converter can achieve low total harmonic distortion (THD) on the input current and the power pulsation decoupling function between the input and output sides, which allows low output voltage ripple even on a small output energy buffer at the same time using an active buffer. Therefore, the proposed converter does not require large smoothing capacitors or large smoothing inductors. The buffering energy is stored by a small capacitor, which controls the variation of the capacitor voltage through the active buffer. In this paper, the fundamental operations of the proposed converter are investigated experimentally. The experimental results reveal that the input current THD is 1.44%, the rate of the output voltage ripple is 6.33%, and the input P.F. is over 99%. In addition, a maximum efficiency of over 96% is obtained for a 750-W prototype converter. [ABSTRACT FROM PUBLISHER]

Control strategy and loss evaluation is discussed for a proposed dc/ac two-stage boost converter using the neutral point of a motor. The proposed converter consists of a small boost chopper and a three-phase inverter, which has a boost-up function from the use of the leakage inductance of a motor, instead of a boost-up reactor, for dc to ac conversion. A six-step operation strategy is proposed for the circuit. When the inverter part outputs a square waveform of 180^\circ, the input current has a distortion because the neutral point voltage of the motor fluctuates at a frequency three times the output frequency. The input current is also shown distorted due to the neutral point voltage fluctuation. Feedforward compensation is proposed to reduce the input current fluctuation. In addition, the dc current in the proposed circuit is imposed into the phase current of the motor. Loss evaluation is therefore implemented to investigate the influence of the imposed dc current on the experimental results. Also, finite-element method was used to analyze the motor loss for a 1.5-kW interior-permanent-magnet motor. [ABSTRACT FROM PUBLISHER]

This paper proposes a zero-voltage ride-through (ZVRT) method and an LCL filter design method to meet the fault ride-through (FRT) requirements for a single-phase grid-connected inverter with a minimized LCL filter. A high inverter output current overshoot occurs at a grid voltage sag and a grid voltage recovery, when a low-inductance LCL filter design is employed in order to minimize the filter volume. In order to suppress the current overshoot, a high-speed gate-block operation and the design method of the minimized LCL filter are proposed. In particular, the filter design considers the delay time in the gate-block operation in order to clarify the reduction limitation of the inductance in the LCL filter. As a result, the maximum inverter output current overshoot is suppressed to 146% by the high-speed gate-block operation and the designed LCL filter, where the impedances of an interconnected inductor and a filter inductor are 1.0% and 0.78% of the inverter normalized impedance, respectively. Therefore, it is possible to meet the FRT requirements with the proposed ZVRT method even with the minimized LCL filter. [ABSTRACT FROM AUTHOR]

This paper proposes a current control method for discontinuous current mode (DCM) in order to achieve the same control performance as continuous current mode (CCM) in a boost converter. By utilizing the duty ratio at the previous calculation period to compensate for a DCM nonlinearity, the controller, which is designed for CCM, can also be used in DCM. In the frequency analysis, the cutoff frequency of the proposed DCM current control agrees exactly to the design value, which is 2 kHz, whereas the cutoff frequency of the conventional DCM current control results in high error of 47.5%. In the current step response experiment with a 360-W prototype and the switching frequency of 20 kHz, the experimental DCM current response almost agrees with the conventional CCM current response, which are 380-μs rise time for both CCM and DCM, 9% and 8% overshoot for CCM and DCM, respectively. Furthermore, the computation time of the proposed DCM current control is shorter 35% than the conventional DCM current control. [ABSTRACT FROM AUTHOR]

This paper proposes a new circuit configuration and a control scheme for a single-phase current-source inverter with a power decoupling circuit which is called as the active buffer. The proposed inverter achieves a low-dc-input voltage ripple and also provides a sinusoidal current that can achieve unity power factor, without large passive components in the dc bus such as smoothing inductors and electrolytic capacitors. These components are conventionally required in order to decouple the power pulsation caused by the single-phase power source. In this paper, the fundamental operations of the proposed inverter are demonstrated experimentally. From the experimental results, the input voltage ripple is 8.87%, and the output current total harmonic distortion is 4.24%. In addition, an output power factor of 99% and a maximum efficiency of 94.9% are obtained. Finally, it is confirmed that the maximum power densities of the conventional circuit and the proposed circuit are 2.75 kW/L at the switching frequency of 70 kHz and 4.86 kW/L at the switching frequency of 80 kHz, respectively. [ABSTRACT FROM AUTHOR]

In the present, a power decoupling method without additional component is proposed for a dc to single-phase ac converter, which consists of a flying capacitor dc/dc converter (FCC) and the voltage source inverter (VSI). In particular, a small flying capacitor in the FCC is used for both a boost operation and a double-line-frequency power ripple reduction. Thus, the dc-link capacitor value can be minimized in order to avoid the use of a large electrolytic capacitor. In addition, component design, of, e.g., the boost inductor and the flying capacitor, is clarified when the proposed control is applied. Experiments were carried out using a 1.5-kW prototype in order to verify the validity of the proposed control. The experimental results revealed that the use of the proposed control reduced the dc-link voltage ripple by 74.5%, and the total harmonic distortion (THD) of the inverter output current was less than 5%. Moreover, a maximum system efficiency of 95.4% was achieved at a load of 1.1 kW. Finally, the high power density design is evaluated by the Pareto front optimization. The power densities of three power decoupling topologies, such as a boost topology, a buck topology, and the proposed topology are compared. As a result, the proposed topology achieves the highest power density (5.3 kW/dm3) among the topologies considered herein. [ABSTRACT FROM AUTHOR]