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This letter demonstrates an on-silicon integrated thin film coupled inductor using a novel cascade matrix concept to suit multiphase integrated voltage regulator (IVR) applications. The novel cascade matrix coupled (CMC) stripline inductor facilitates all-phase-coupled configuration to reduce the phase ripple current in IVRs. It also shows excellent scalability and neat floor planning. Moreover, the proposed CMC inductor uses double layer metal scheme for windings and interconnects, which significantly reduces the ac winding resistance. A four-phase CMC inductor has been successfully fabricated on-silicon substrate and characterized, which uses conventional thin film magnetic core deposition process to achieve in-plane magnetic uniaxial anisotropy. The device occupies 3.2 × 1.7 mm2 floor area and provides 19.5 nH phase inductance with 120 mΩ dc resistance. The saturation current for each phase is up to 0.4 A when the phase inductance drops by approximately 20%. The coupling coefficient between any two phases of the proposed CMC inductor is 0.27, much higher and more controllable than that of toroid core-based coupled inductors. [ABSTRACT FROM AUTHOR]

Coupled inductors offer significant advantages over their uncoupled counterparts; however, with these advantages come a number of additional design caveats. The factors affecting the design and optimization of coupled stripline microinductors for PwrSoC applications are outlined, which include device area, the number of coupled phases, duty cycle, paralleling of coupled inductors, switching frequency, as well as thermal and saturation constraints. Results of this analysis are presented and discussed along with guidelines for the design of coupled stripline microinductors, which show that paralleling coupled inductors is the best route toward higher output current. Analytical models predict a peak inductor efficiency of 86.8% and 86.3% for fabricated 3 and 5-phase coupled stripline microinductors with an Ni45Fe55 core, respectively. Models are verified by measurements on prototype 3 and 5-phase converters with parallel coupled stripline microinductors over a range of operating conditions. [ABSTRACT FROM AUTHOR]

In this paper, models that account for the duty cycle and phase shift angle of the applied phase voltages in coupled stripline microinductors are presented and are shown to have a significant impact on harmonic current amplitudes and therefore microinductor efficiency. The impact of a high coupling factor between two windings surrounded by a single core is also investigated. The models are validated using finite-element analysis and measurements. A three-phase-coupled microinductor has been fabricated with a Ni45Fe55 core and analyzed for a number of operating conditions. A prototype 1.6 W, three-phase converter utilizing this inductor has also been measured and is discussed in detail. The coupled microinductor is predicted to have a peak efficiency of 86.6% at 20 MHz in the prototype circuit. [ABSTRACT FROM AUTHOR]

Inductor-on-silicon research to date has focused on optimizing technologies for maximum power density and efficiency, with most design procedures based on computationally intensive methods. In this paper, a simple and intuitive method for designing microinductors based on a given dc–dc converter specification, which includes accurate models for all loss components, is presented. A detailed examination of variations in designs to realise the same circuit performance is presented. Finally, finite element analysis simulations demonstrating the accuracy of the models are given, along with measured results. [ABSTRACT FROM AUTHOR]

This paper examines the process challenges in developing high aspect-ratio copper structures for improving microinductor performance. With increased miniaturization, increasing windings losses become a major challenge limiting the microinductor efficiency. It was also identified that within constraint footprints coil thickness to spacing ratio increase can reduce dc resistance significantly. In this paper, we present a reliable process for developing high aspect ratio ( $\sim 5.8$ ) resist moulds for copper electrodeposition. This resist provided coil spacings 10 $\mu $ m for 58 $\mu $ m resist thickness; this in turn reduces the dc resistance of a typical microinductor by more than 17% when compared with a similar device reported previously. [ABSTRACT FROM AUTHOR]

Thin-film Si-integrated inductors with closed cores have different magnetic field distributions in the winding window space compared to the inductors with unclosed cores. One-dimensional methods are no longer applicable for these inductors to calculate the ac resistance. Based on the analysis of the magnetic field distribution of the devices, a 2-D field solution was developed, which leads to an improved 2-D method to calculate the ac resistance of the device. High accuracy of this new approach has been verified by finite-element analysis, while 1-D methods can lead to significant errors. [ABSTRACT FROM AUTHOR]

What is the future of integrated inductor design on silicon for power conversion applications at frequencies up to 100 MHz—is it magnetic-core or air-core inductors. This study presents measured results for two microfabricated inductors (magnetic core and air core), which have been designed to operate at 20 MHz and occupy a substrate area of less than 10 mm^2. The inductor technology and design are briefly discussed. An optimized inductor design study is, then, presented. Both magnetic-core and air-core inductor designs are compared and evaluated, in terms of inductance and efficiency per unit area for frequencies up to 100 MHz. The design of the microinductors is discussed and an analytical design optimization program is used to model the devices for the maximum efficiency and inductance. The introduction of laminations with high-frequency core inductors will also be examined within the study. A 100 MHz magnetic-core inductor design with three laminations gives a 36 nH inductance, with 96.4% efficiency and an area of 3 mm^2. A comparable air-core design also gives a 36 nH inductance, with 93.45% efficiency and an area of just 2.6 mm^2. [ABSTRACT FROM AUTHOR]

This paper presents the design of miniaturized bond wire transformers assembled with standard IC bonding wires and NiZn and MnZn ferrite toroidal cores. Several prototypes are fabricated on a printed circuit board substrate with various layouts in a 4.95\; mm \times 4.95\; mm area. The devices are modeled by analytical means and characterized with impedance measurements over a wide frequency range. Experimental results on 1:38 device show that the secondary self-inductance increases from 0.3 μH with air-core to 315 μH with ferrite core; the coupling coefficient improves from 0.1 with air-core to 0.9 with ferrite core; the effective turns ratio enhances from 0.5 with air-core to 34 with ferrite core. This approach is cost effective and enables a flexible design of efficient micromagnetics on top of ICs with dc inductance to resistance ratio of 70 μH/Ω and an inductance per unit area of 12.8 μH/mm2 up to 0.3 MHz. The design targets the development of bootstrap circuits for ultralow voltage energy harvesting. In this context, a low-voltage step-up oscillator suitable for thermoelectric generator sources is realized with a commercial IC and the proposed microtransformers. Experimental measurements on a discrete prototype report that the circuit bootstraps from voltages down to 260 mV and outputs a dc voltage of 2 V. [ABSTRACT FROM AUTHOR]

In an integrated power microinductor, the size and shape of the magnetic material will have a relationship to the permeability and inductance of the device. To demonstrate these effects, a set of inductors with closed Ni45Fe55 films were fabricated having similar structures but different footprint sizes and aspect ratios (ARs). Magnetic and electrical characterization was performed on the devices to determine magnetic properties, and in both measurements the same relationship between film shape and magnetic anisotropy is observed. Micromagnetic shape anisotropy simulations were used to predict this behavior and correlate with the experimentally determined parameters. The AR of the film is determined to have a strong influence on the anisotropy and permeability of the magnetic film via shape demagnetization effects which is shown to be a significant variation from the as-deposited magnetic material parameters. [ABSTRACT FROM AUTHOR]

In this work a stacked winding thin film magnetic core microinductor is proposed to improve the ratio of inductance to dc resistance (DCR). This article also describes an improved ac winding loss model accounting for the asymmetric 2-D magnetic fields present within the device. Two six-turn single layer and stacked winding devices are fabricated, and small signal measurements are presented with dc inductance of 150 nH and DCR of $0.35~\Omega $ for the stacked winding inductor, and with DCR of $0.47~\Omega $ for the single winding inductor. In this case, the total DCR of stacked winding inductor is reduced by approximately 25% compared with the corresponding single layer structure with an equivalent inductance and device area. [ABSTRACT FROM AUTHOR]

Microfabricated inductors experience increasing interest and research activity because of their high potential in buck converters for power supply in package and power supply on chip applications. This paper details the modeling and optimization of microfabricated racetrack inductors. The analytical expressions derived characterize inductance, efficiency, and power density based on geometrical parameters, inductor current, and switching frequency. An accurate analysis of the inductor current that includes the impact of losses is performed to determine the switching frequency, the ac copper losses, and the core losses. The presented model is compared to finite element method simulations and reported results of three microfabricated inductors. Finally, the optimum tradeoff between efficiency and power density is identified using the Pareto front, which results from the evaluation of a large number of microfabricated inductors in the design space defined by the application. [ABSTRACT FROM AUTHOR]