Search

In this article, we have evaluated the merits of monolithically cointegrated alternate channel complementary metal-oxide-semiconductor (CMOS) device architecture, utilizing tensile strained germanium ($\boldsymbol {\varepsilon }$ -Ge) for the p-channel FinFET and variable indium (In) compositional InxGa1-xAs ($0.10\le {x} \le0.53$) for the n- channel FinFET. The device simulation models were calibrated using the experimental results of Ge and InGaAs FinFETs and subsequently transferred to the cointegrated Ge and InxGa1-x As structure while keeping the device simulation parameters fixed. The device parameters, such as ${V}_{\text {T}}$ , ${I}_{\text {on}}$ , ${I}_{\text {off}}$ , and subthreshold-swing (SS), were determined for identical fin dimensions for n- and p-channel FinFETs as a function of In composition that alters the tensile strain in Ge. These parameters are controllable during the heteroepitaxial growth by varying In composition in InxGa1-xAs. $\boldsymbol {\varepsilon }$ -Ge p-FinFET is shown to be superior in terms of SS and ${I}_{\text {on}}/{I}_{\text {off}}$ ratio compared with other competing architectures. The cointegrated architecture of CMOS inverter exhibited an optimum performance over a range of In compositions from 20% to 40% while driving fan-out fan-out 1 (FO-1) and FO-4 load configurations. In addition, the CMOS inverter with symmetric rise and fall times as well as noise-immune functionality demonstrated 150 GHz of operating frequency with 30-nW total power dissipation at 20% In composition, and hence a superior power-delay-product comparable with International Technology Roadmap for Semiconductors (ITRS) standards. Moreover, the three-stage CMOS ring oscillator performance was evaluated with various In compositions to be stable and power efficient. Thus, the cointegrated approach has a potential to: 1) simplify large-scale CMOS integration and 2) be compatible with optoelectronic materials. [ABSTRACT FROM AUTHOR]

Novel strain-engineered staggered gap Ge/InxGa1–xAs heterojunction tunnel FETs (H-TFETs) are proposed and theoretically evaluated. Modulation of the indium alloy composition at the source–channel heterointerface resulted in 18.6\times and 16.9\times enhancement in I\mathrm{\scriptscriptstyle ON} for n- and p-channel Ge/InxGa1–xAs H-TFETs, respectively, as compared with strained Ge homojunction TFETs (p+-Ge/i-Ge/n+-Ge). The n-type H-TFETs (p+-Ge/i-InxGa1–xAs/n+-InxGa1–xAs) exhibited superior leakage suppression due to a larger tunneling barrier at the channel–drain interface. Moreover, the p-type H-TFETs (n+-InxGa1–xAs/i-Ge/p+-Ge) demonstrated a significant enhancement in I\mathrm{\scriptscriptstyle ON} due to an unequal shift in the conduction band edge as a result of doping-induced bandgap narrowing. The simulated tensile-strained Ge/InxGa1–xAs H-TFETs show a great promise for ultralow-power switches with high ON-state and low OFF-state current, providing a new path for low-power complimentary TFET logic. [ABSTRACT FROM PUBLISHER]

Abstract: The application of an In0.7Al0.3As window layer material on the properties of lattice-mismatched (LMM) single-junction (SJ) In0.69Ga0.31As thermophotovoltaic (TPV) cells grown by solid source molecular beam epitaxy (MBE) was studied as an alternative to conventional InAsP window layers. For these 0.60eV bandgap SJ devices, high performance was achieved, displaying open-circuit voltage of 355mV, power density of 0.532W/cm2 and a fill factor of 66.5% measured at a current density value of 2.26A/cm2. The measured internal quantum efficiencies were close to ∼100% at wavelengths between approximately 1.2–1.4mm, suggestive that low carrier recombination rates in the vicinity of this alternative In0.70Al0.30As/In0.69Ga0.31As window/emitter interface has been achieved. The quantum efficiency data coupled with the device parameters show that InAlAs can be successfully substituted for conventional InAsP window layers in metamorphic TPV devices. By using an interface consisting solely of III-As alloys for the window/emitter material pairing as opposed to the conventional InAsP/InGaAs window/emitter design, this approach avoids the problematic III-P/III-As interface transition for MBE growth of TPV devices that has been shown to impact carrier collection efficiency [Hudait MK, Lin Y, Palmisiano MN, Ringel SA. 0.6-eV band gap In0.69Ga0.31As thermophotovoltaic devices grown on InAs y P1− y step-graded buffers by molecular beam epitaxy. IEEE Electron Dev Lett 2003;24(9):538–40]. [Copyright &y& Elsevier]

DC and high-frequency device characteristics of In[sub0.7]Ga[sub0.3]As and InSb quantum-well field-effect transistors (QWFETs) are measured and benchmarked against state-of- the-art strained silicon (Si) nMOSFET devices, all measured on the same test bench. Saturation current (I[subon]) gain of 20% is observed in the In[sub0.7]Ga[sub0.3]As QWFET over the strained Si nMOSFET at (V[subg] - V[subt]) = 0.3 V, V[subds] = 0.5 V, and matched I[suboff], despite higher external resistance and large gate-to-channel thickness. To understand the gain in I[subon], the effective carrier velocities (V[subeff]) near the source-end are extracted and it is observed that at constant (V[subg] - V[subt]) = 0.3 V and V[subds] = 0.5 V, the V[subeff] of In[sub0.7]Ga[sub0.3]As and InSb QWFETs are 4-5x higher than that of strained silicon (Si) nMOSFETs due to the lower effective carrier mass in the QWFETs. The product of V[subeff] and charge density (n[sub8]), which is a measure of "intrinsic" device characteristics, for the QWFETs is 50%-70% higher than strained Si at low-voltage operation despite lower n[sub8] in QWFETs. Calibrated simulations of In[sub0.7]Ga[sub0.3]As QWFETs with reduced gate-to-channel thickness and external resistance matched to the strained Si nMOSFET suggest that the higher V[subeff] will result in more than 80% I[subon] increase over strained Si nMOSFETs at V[subds] = 0.5 V, (V[subg] - V[subt]) = 0.3 V, and matched I[suboff], thus showing promise for future high-speed and low-power logic applications. [ABSTRACT FROM AUTHOR]

Abstract: In x Ga1− x As III–V compound semiconductor metal–oxide–semiconductor field-effect transistors have become a popular topic recently due to the higher drift velocity, and lower effective mass of the In x Ga1− x As materials. The impact of In content on the accumulation and inversion behaviors of the Al2O3/In x Ga1− x As capacitors is investigated in this study. For the various In x Ga1− x As materials studied, the Al2O3/InAs MOS system showed the strongest inversion phenomena due to the shorter response time of minority carrier of InAs compared to other In x Ga1− x As materials. Also, very low gate leakage current in the 10−8 A/cm2 range was observed for these capacitors. These results demonstrate that Al2O3/InAs MOS system with strong inversion phenomena and low leakage gate current is potential candidate for future high-performance low power logic MOSFET applications. [Copyright &y& Elsevier]