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As very large-scale integration technology shrinks to fewer tracks per standard cell, e.g., from 10 to 7.5-track libraries (and lesser for 7 nm), there has been a rapid increase in the usage of multiple-row cells like two- and three-row flip-flops, buffers, etc., for design closure. Additionally, the usage of multibit flip-flops or flop trays to save power creates large cells that further complicate critical design tasks, such as placement. Detailed placement happens to be a key optimization transform, which is repeatedly invoked during the design closure flow to improve design parameters, such as wirelength, timing, and local wiring congestion. Advanced node designs, with hundreds of thousands of multiple-row cells, require a paradigm change for this critical design closure transform. The traditional approach of fixing multiple-row cells during detailed placement and only optimizing the locations of single-row standard cells can no longer obtain appreciable quality of results. It is imperative to have new techniques that can simultaneously optimize both multiple- and single-row height cell locations during detailed placement. In this paper, we propose a new density-aware detailed placer for heterogeneous-sized netlists. Our approach consists of a chain move scheme that generalizes the movement of heterogeneous-sized cells, a nested dynamic programming-based approach for ordered double-row placement and a network flow-based formulation to solve ordered multiple-row placement for wirelength and density optimization. Experimental results demonstrate the effectiveness of these techniques in wirelength minimization and density smoothing compared with the most recent detailed placers for designs with heterogeneous-sized cells. [ABSTRACT FROM PUBLISHER]

Along with the progress of very-large-scale-integration technology, buffer insertion plays an increasingly critical role on affecting circuit design and performance. Traditional buffer insertion algorithms are mostly net based and therefore often result in suboptimal delay or unnecessary buffer expense due to the lack of global view. In this paper, we propose a novel path-based-buffer-insertion (PBBI) scheme which can overcome the weakness of the net-based approaches. We also discuss some potential difficulties of the PBBI approach and propose solutions to them. A fast estimation on buffered delay is employed to improve the solution quality. Gate sizing is also considered at the same time. Experimental results show that our method can efficiently reduce buffer/gate cost significantly (by 71% on average) when compared to traditional net-based approaches. To the best of our knowledge, this is the first work on path based buffer insertion and simultaneous gate sizing. [ABSTRACT FROM AUTHOR]

Shrinking process geometries and the increasing use of intellectual property components in system-on-chip designs give rise to new problems in routing and buffer insertion. A particular concern is that cross-chip routing will require multiple clock cycles. Another is the integration of independently clocked components. This paper explores simultaneous routing and buffer insertion in the context of single- and muitiple-clock domains. We present two optimal and efficient polynomial algorithms that build upon the dynamic programming fast path framework. The first algorithm solves the problem of finding the minimum latency path for a single-clock domain system. The second considers routing between two components that are locally synchronous yet globally asynchronous to each other. Both algorithms can be used for interconnect planning. Experimental results verify the correctness and practicality of our approach. [ABSTRACT FROM AUTHOR]

Buffer insertion is a fundamental technology for very large scale integration interconnect optimization. This work presents the repeater insertion with adaptive tree adjustment (RIATA) heuristic that directly extends van Ginneken's classic algorithm to handle blockages in the layout. Given a Steiner tree containing a Steiner point that overlaps a blockage, a local adjustment is made to the tree topology that enables additional buffer insertion candidates to be considered. This adjustment adapts to the demand on buffer insertion and is incurred only when it facilitates the maximal slack solution. RIATA can be combined with any performance-driven Steiner tree algorithm and permits various solution search schemes to achieve different solution quality and runtime tradeoffs. Experiments on several large nets confirms that high-quality solutions can be obtained through this technique with greater efficiency than simultaneous approaches. [ABSTRACT FROM AUTHOR]

Assesses the implications of fixed terminals for hypergraph partitioning heuristics for integrated circuits design. Effect of fixed terminals on instance difficulty; Partitioners for the fixed-terminals regime; Conclusions.

Thank you for the continued support to the journal as readers and volunteers. We are grateful for the opportunity to serve at the helm of TCAD for another term. We would like to thank our Associate Editors for the 2014–15 term for their selfless service to our community. Their professionalism and dedication has been a significant factor in enhancing the prestige of the journal and in reducing the review cycle. While many of them continue for their new term, some have retired after their distinguished contributions serving multiple previous terms. We would like to extend a hearty welcome to our new associate editors who add geographical and technical diversity to our board. We have a significantly larger editorial board than the last term to keep the review burden on our associate editors reasonable and to add expertise into new growth areas in our field. [ABSTRACT FROM PUBLISHER]

Editorial. Introduces a series of papers that were presented at the International Symposium on Physical Design (ISPD) held in Del Mar, California in 2002. Exchange of ideas and results in critical areas related to the physical design of very large scale integration systems; Interconnect performance prediction and optimization; Design for manufacturability; Floor planning; Congestion estimation.

Physical design is one of the key areas in modern integrated circuit design, and computer-aided design research in this area has shown a new resurgence after the advent of deep submicrometer effects and the accompanying stringent performance constraints. Effects related to increased interconnect congestion effects, reduced noise margins, and growing on-chip inductance have resulted in technically challenging problems in areas such as floorplanning, placement, routing, and performance prediction. In addition, the ability to pack ever more transistors into less silicon challenges the scalability of existing algorithms. In addition to that, the article presents various other related information.