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Interconnect congestion estimation plays an important role in the physical design of integrated circuits. Fast congestion analysis prior to global routing enhances the placement quality and improves the routability for the subsequent routing phases. This article presents a novel congestion estimation method for a wire layout with bounded detours and bends. Experimental results on benchmarks demonstrate the efficiency and accuracy of our approach. [ABSTRACT FROM AUTHOR]

For nanometer manufacturing, process variation causes significant uncertainty for circuit performance verification. Statistical static timing analysis (SSTA) is thus developed to estimate timing distribution under process variation. Most existing SSTA techniques have difficulty in handling the non-Gaussian variation distribution and nonlinear dependence of delay on variation sources. To address this problem, we first propose a new method to approximate the max operation of two non-Gaussian random variables through second-order polynomial fitting. With such approximation, we then present new non-Gaussian SSTA algorithms for three delay models: quadratic model, quadratic model without crossing terms (semiquadratic model), and linear model. All the atomic operations (max and sum) of our algorithms are performed by closed-form formulas; hence, they scale well for large designs. Experimental results show that compared to the Monte Carlo simulation, our approach predicts the mean, standard deviation, skewness, and 95% percentile point within 1%, 1%, 6%, and 1% error, respectively. [ABSTRACT FROM AUTHOR]