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This introduction to the special series discusses the emerging field of harsh-environment-capable chips, or harsh chips. It also introduces the first two Harsh Chips articles in the issue. [ABSTRACT FROM PUBLISHER]

The author reflects on the changes to be made by "Micro" magazine on its year-end issue in terms of its image, quality, and readership since 2003. The impacts of the emergence of the multicore chips generation on software and applications are presented. Multimedia and mobile communications are part of the new applications that contribute to the growth of high-performance processor chips designed for nonconvential markets. The plans of "Micro" for the coming years under a new editorship are featured.

The article looks into the significance of workload characterization as an important aspect in microarchitecture design. The author contended that it is crucial for the design team to understand the application space for the product during the project's early stages. The performance modeling team needs to adopt an intelligent and representative sampling policy to cut down on simulation time. It is necessary to propose a set of measurements when developing a representativeness check metric for sampled traces. The author discusses some of the workload characteristics such as dynamic-instruction frequency mix and dependence distances.

The article presents information on the use of electronic circuit design in the information technology sector. Energy efficiency has been a key design constraint for microprocessor development teams since the late 1990s. In fact, such a basic paradigm shift has been in the works for a few years, with the introduction of IBM's dual-core Power4 chip in 2000. The industry in general has recently made a clear shift toward lower frequency, multicore architectures for general-purpose high-performance microprocessors. Intel, AMD, and Sun Microsystems have all announced future product roadmaps that embrace the multicore paradigm. Although such a shift has enabled design groups to keep going for a little while, the need for building power efficiency into the chip's non-core components continues unabated. Academic research in low-power design techniques have evolved from lower-level issues related to the underlying device and circuit technologies to higher-level knobs available in the microarchitecture, architecture, and even the application and software layers.

Power7 implements several new adaptive power management techniques which, in concert with the EnergyScale firmware, let it proactively exploit variations in workload, environmental conditions, and overall system use to meet customer-directed power and performance goals. These innovative features include per-core frequency scaling with available autonomic frequency control, per-chip automated voltage slewing, power consumption estimation, and hardware instrumentation assist. [ABSTRACT FROM PUBLISHER]

The article highlights that the evaluation of overall quality of a microprocessor has become more difficult than before, because the technological advancement has led to rapid increase in the number of transistors in a die. Despite the fact that the individual device speeds and overall chip frequencies are lagging, designers are using complex on-chip architecture in an attempt to increase the performance of the chips.

The article focuses on current design practices in the information technology sector. Achieving high performance at affordable power is the overall system goal across a whole range of products that serve the home, entertainment, scientific, and commercial-enterprise segments of the information technology industry. The only problem is that growth in the performance-cost ratio is no longer economically sustainable without major innovations and design paradigm shifts. The trend toward multicore chip designs is an example of a major shift. There are at least two ways of looking at energy-efficient design: meeting a power consumption target at acceptable performance, or meeting a performance target at an acceptable power level. Depending on whether the recurrent energy cost or the dissipation cost is the dominant consideration for viewing things a bit differently. It is probably fair to say that each designer is interested in understanding and practicing energy-efficient design principles in the information technology sector.

The article presents information on the emerging trends of chip-level microarchitecture. One of the trends in high-performance microprocessor chips is the increased level of on-chip integration that the technology has made available. IBM's Power 4 had previously started the trend of multicore designs with a dual-core chip multiprocessor offering. In these future designs, each core or thread may not necessarily aim at delivering the highest frequency or performance that is achievable for the given technology. The power "wall" is definitely a factor that could accelerate this trend, since single-core frequencies might not scale up to meet prior trends. On the other hand, the chip-level power and area budgets especially pertaining to leakage place a natural limit on the number of cores for a given level of core complexity. Of course, in some markets, single thread performance might remain the primary driver of chip-level microarchitecture design. Here, to meet performance targets at affordable cost, cooling and packaging technologies must improve sufficiently to meet the challenge. Finally the article also discusses some of the latest advances, trends, and challenges in microprocessor design.

This article focuses on new challenges facing chip-level microarchitects and designers. The article also addresses issues that have surfaced recently and are likely to face the industry for a while. These issues concern the problem of escalating power densities and temperatures in future CMOS microchips. The power and power density limits in air-cooled systems make the outlook for future performance growth uncertain because of the pressure on package and cooling costs. Higher chip and device junction temperatures threaten to degrade lifetime reliability as well as delivered performance.

Introduces a series of articles on microelectronic chip and silicon system design. Challenges facing microchip designers; Inherent problems in communication systems; Issue of widening gap between memory and central processing unit.

Introduces a series of articles related to on-chip integration within complex system-on-a-chip design, including the application of silicon-on-insulator technology in smart cards.

Introduces several articles on integrated circuits and silicon systems design in the March/April 2003 issue of 'IEEE micro.'