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Ferroelectric tunnel junction (FTJ) is able to store non-volatile data in the spontaneous polarization direction of ferroelectric tunnel barrier. Recent progress has demonstrated its great potential to build up the next generation non-volatile memory and logic (NVM and NVL) thanks to the high OFF/ON resistance ratio, fast operation speed, low write power, non-destructive readout and so on. In this paper, we present the first physics-based compact model for Co/BTO/LSMO FTJ nanopillar, which was reported experimentally to exhibit excellent NVM performance. This model integrates related physical models of tunnel resistance, static switching voltage and dynamic switching delay. Its accuracy is shown by the good agreement between numerical model simulation and experimental measurements. This compact model has been developed in Verilog-A language and validated by single-cell simulation on Cadence Virtuoso Platform. Hybrid simulations based on 40 nm-technology node of FTJ memory arrays and non-volatile full adder were performed to demonstrate the efficiency of our compact model for the simulation and analysis of CMOS/FTJ integrated circuits. [ABSTRACT FROM AUTHOR]

Magnetic tunnel junctions (MTJ) are considered as one of the most promising candidates for the next generation of nonvolatile memories and programmable logic chips. Spin transfer torque (STT) in CoFeB/MgO/CoFeB MTJs with perpendicular magnetic anisotropy (PMA) exhibits noticeable performance enhancements compared to that with In-plane magnetic anisotropy, particularly in terms of thermal stability, critical current for switching, access speed and power consumption. However, the STT switching of MTJ has been revealed stochastic, which results from unavoidable thermal fluctuations of magnetization. This leads to the occurrence of write errors which deeply affects the reliability of hybrid CMOS/MTJ circuits. In this paper, we present the first spice-compact model of CoFeB/MgO/CoFeB structure PMA-MTJ integrating STT stochastic behaviors. Depending on the relative magnitude between the switching current (I) and the critical current (Ico), the STT stochastic behaviors of this PMA-MTJ can be categorized into two regions: Sun model (I>Ico) and Neel-Brown model (I<0.8Ico). The Monte-Carlo simulations for single cell and hybrid CMOS/MTJ circuits show the stochastic behaviors in both writing and sensing operations. This model can be very useful for investigating the reliability issues during the design and simulation before process fabrication. [ABSTRACT FROM AUTHOR]

A new path to frame low power, high-density and fast integrated circuits has been rolled out by the observation of current-induced domain wall (DW) motion in magnetic track. As an advanced extension of this mechanism, high performance racetrack memory can be built up combining with magnetic tunnel junction (MTJ) read and write heads. The rapid progress of CoFeB/MgO perpendicular magnetic anisotropy (PMA) shows that the PMA MTJ can be scaled down to 20 nm while keeping fast data access. These recent discoveries allow us to design an ultra-high density content addressable memory (CAM), one of the most important applications of MRAM. The mainstream CAMs suffer from high power and large area as its conventional structure is composed of numerous large-capacity SRAM blocks in order to provide fast data access. MRAM based non-volatile CAMs have been proposed to relive the power consumption, however the density issue cannot be surmounted due to the large switching currents. In this paper, we present a design of NOR-type CAM based on DW motion in PMA magnetic tracks. The CMOS switching and sensing circuits are globally shared to optimize the cell area down to 6 F^2/bit; the complementary dual track allows the local sensing and faster data search speed while keeping low power. By using an accuracy spice model of PMA racetrack memory and CMOS 65 nm design-kit, mixed simulations have been performed to demonstrate its functionality and evaluate its high performance. [ABSTRACT FROM PUBLISHER]

Recently, ultra-low power circuits based on logic-in magnetic tunnel junction (MTJ) memory structure have been studied thanks to its non-volatility, infinite endurance, high access speed, and easy integration with CMOS process. However, this type of circuit suffers from low reliability both in memory cell and sensing amplifier circuits, which greatly limits its practical applications for logic computation. In this paper, we present a new design of magnetic full adder (MFA) to overcome this issue based on the thermally assisted switching (TAS) MTJ cell and pre-charge sensing amplifier (PCSA) circuit. By using CMOS 65 nm design kit and a precise TAS-MTJ model, mixed simulations have been performed to demonstrate its high reliability keeping low power and small die area. [ABSTRACT FROM PUBLISHER]

The current challenges of spintronic devices are the large power and long latency for magnetic switching. Current-induced domain wall (DW) motion is a new switching mechanism promising low-power, high-density, and high-speed circuits. It was first studied to build “race track” memory, which is considered as one of the most emerging technologies for future stand-alone memory. Based on the 3-D hybrid integration above CMOS circuits and using magnetic tunnel junction (MTJ) as the write/read heads, DW motion can be advantageously extended to logic and embedded memory applications. In this paper, we present the first DW shift register-based lookup-table circuit to build reconfigurable logic, which may nearly halve the die area compared with conventional SRAM-LUT by sharing a number of subcircuits and suggest some new functions such as multicontext configuration and run-time reconfiguration for further performance improvement. By using a DW electrical model and CMOS 65-nm design kit, its performances such as low power and high computing/reconfiguration speed have been simulated or calculated. [ABSTRACT FROM AUTHOR]