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Abstract: As the electronics industry continues its efforts in miniaturizing the integrated circuit (IC), an IC chip with copper/low-k stacked Back End of Line (BEoL) structures has been developed for reducing R–C delay in order to obtain high-speed signal communication. However, its reliability might become a concern owing to the considerably lower adhesive strength, as well as the greater coefficient of thermal expansion (CTE) of the low-k materials. In this paper, the global–local finite element method, specified boundary condition (SBC) method, is employed as a bridge to estimate the impact from package level to the deep submicron BEoL structure of the flip chip package. The results show that the defect in the stacking structure at the center of the silicon has a lower tendency to crack than that at the corner region. In addition, the higher underfill CTE shows the disadvantage of the defect. [Copyright &y& Elsevier]

Abstract: As the progress of the semiconductor process develops to achieve miniaturization and attain better performances for the electronic device, next-generation IC chips with deep sub-micron Cu/low-k stacked structures adopting the fabrication of (dual) damascene are developed to meet the urgent requirements of reducing high RC delay; the purpose of this is to obtain high-speed signal communication. However, due to poor adhesion and intrinsically lower fracture toughness of low-k materials as well as process loading that introduces flaws and delaminations, the phenomenon of crack growth is observed. To investigate the large scale difference problem, such as the back end of line (BEoL) structure to the silicon chip, a special multi-scale finite element simulation technology, global–local finite element method, is used to deal with this issue. The interfacial crack in the BEoL structure is modeled using the global–local technique. The chemical vapor deposition (CVD) process that induced loading to a micro crack in the interface between etch stop layer and metal track layer (ESL/Mx interface) will also be discussed through a statistical factorial design method in order to understand the crack growth phenomena that might occur during the BEoL process. [Copyright &y& Elsevier]

Abstract: As the electronics industry continues its efforts in miniaturizing the integrated circuit (IC), an IC chip with copper/low-k stacked back end of line (BEoL) structures has been developed for reducing RC delay in order to obtain high-speed signal communication. However, its reliability might become a concern due to the considerably lower adhesive strength as well as greater coefficient of thermal expansion (CTE) of the low-k materials. In this paper, the four-point bending technique is used to quantify the adhesion energy (G C). The global local finite element method, including the specified boundary condition (SBC) method and the multi-point constrain (MPC) method, is validated by the four-point bending experiment and is employed as a bridge to estimate the impact from package level to the deep sub-micron BEoL structure of the plastic ball grid array (PBGA) package. A crack driving force of 1.8J/m2 acting on the BEoL structure is obtained when the curing process of the moulding compound is performed. [Copyright &y& Elsevier]