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This paper proposes an adaptive RF front-end (RFFE) architecture that uses an electrical-balance duplexer (EBD) and tuned surface acoustic wave (SAW) resonators to enable adaptive dual-frequency isolation suited for LTE’s frequency-division duplex (FDD) mode of operation. Alternatively, in the in-band full-duplex (IBFD) mode, the EBD cancels the in-band TX self-interference directly at RF for increased channel capacity. Furthermore, the EBD’s balance network is optimized to reduce the TX insertion loss (IL) below the nominal 3-dB limit in the FDD mode. A 0.18- \mu \textm SOI CMOS prototype implements the EBD, low-noise amplifier, and SAW-tuning capacitor banks. The chip is mounted to a module substrate together with the SAWs and matching components. The RFFE achieves >50-dB dual-frequency isolation and 2.6–3.4-dB TX IL in FDD mode, has +58/+42-dBm TX/RX-path IIP3 for an increased IBFD-link budget and handles up to +27.5-dBm TX power in both modes. [ABSTRACT FROM PUBLISHER]

A 5 bit 1.75 GS/s ADC using a factor 2 dynamic folding technique is presented. The 2X folding lowers the number of comparators from 31 to 16, simplifies encoding and reduces power consumption and area. The comparators in this converter are implemented with built-in references and calibration to further reduce power consumption. INL and DNL after calibration are smaller than 0.3 LSB, with an SNDR of 29.9 dB at low frequencies, and above 27.5 dB up to the Nyquist frequency. The converter consumes 2.2 mW from a 1 V supply, yielding a FoM of 50 fJ per conversion step and occupies 0.02 mm2 in a 90 nm 1P9M digital CMOS process. [ABSTRACT FROM AUTHOR]

The commercial potential of the 60 GHz band, in combination with the scaling of CMOS, has resulted in a lot of plain digital CMOS circuits and systems for millimeter-wave application. This work presents a 90 nm digital CMOS two-path 52 GHz phased-array receiver, based on LO phase shifting. The system uses unmatched cascading of RF building blocks and features gain selection. A QVCO with a wide tuning range of 8 GHz is demonstrated. The receiver achieves 30 dB of maximum gain and 7.1 dB of minimum noise figure per path around 52 GHz, for a low area and power consumption of respectively 0.1 mm2 and 65 mW. The presented receiver targets 60 GHz communication where beam-forming is required. [ABSTRACT FROM AUTHOR]

Substrate noise generated by the digital circuits on a mixed-signal IC can severely disturb the analog and RF circuits sharing the same substrate. Simulations at the circuit level of the substrate noise coupling in large systems-on-chip (SoCs) do not provide the necessary understanding in the problem. Analysis at a higher level of abstraction gives much more insight in the coupling mechanisms. This paper presents a physical model to estimate and understand the substrate noise generation by a digital modem, the propagation of this noise and the resulting performance degradation of LC tank VCOs. The proposed linearized model is fast to derive and to evaluate, while remaining accurate. It is validated with measurements on two test structures: a reference design and a design with a p+/n-well (digital) guard ring. Both structures contain a functional 40k gate digital modem and a 0.18 µm 3.5 GHz CMOS LC-VCO on a lightly-doped substrate. In both cases, the model accurately predicts the level of the spurious components appearing at the VCO output due to the digital switching activity. The error remains smaller than 3 dB. Finally, we demonstrate how the proposed model enables a systematic and controlled isolation strategy to suppress substrate noise coupling problems. As an example, the model is used to determine suitable dimensions for a digital guard ring. [ABSTRACT FROM AUTHOR]

In mixed analog-digital designs, digital switching noise is an important limitation for the performance of analog and RF circuits. This paper reports a physical model describing the impact of digital switching noise on LC-tank voltage-controlled oscillators (VCOs) in lightly doped substrates. The model takes into account the propagation from the source of substrate noise to the different components in the VCO and the resulting modulation of the oscillator frequency. The model is validated with measurements on a 3.5-GHz LC-tank VCO designed in 0.18-µm CMOS. It reveals that for this VCO, impact occurs mainly via the nonideal metal ground lines for lower frequencies and low tuning voltage and via the integrated inductors for higher frequencies and high tuning voltage. To make the design immune to substrate noise, the parasitic resistance of the on-chip ground interconnect has to be kept as low as possible and inductors have to be shielded. Hence, the developed model allows investigating the dominant mechanisms behind the impact of substrate noise on a VCO, which is crucial information for achieving a substrate noise immune design. [ABSTRACT FROM AUTHOR]

Substrate noise is a major obstacle for mixed-signal integration. Ground bounce is a major contributor to substrate noise generation due to the resonance caused by the inductance and the Vdd — Vss admittance that consists of the on-chip digital circuit capacitance of the MOS transistors, the decoupling, and the parasitics arising from the interconnect. In this paper, we address: 1) the dependence of the Vdd — Vss admittance on the different states of the circuit, the supply voltage, and the interconnect, and 2) the computation of the total supply current with ground bounce. By using a fast and accurate macromodeling approach, the Vdd — Vss admittances of several test circuits are computed with 2%-3% error relative to the values simulated from the complete SPICE level netlist, but several orders of magnitude faster in CPU time and with 10% maximum error relative to the measurements on a test ASIC fabricated in a 0.18-µm CMOS process on a high-ohmic substrate with 18 &Omega · cm resistivity. The measurements also show that this admittance mainly depends only on the connectivity of the gates to the supply rail rather than their connectivity among each other. [ABSTRACT FROM AUTHOR]

Develops an analytic volterra-series-based model for a microelectromechanical systems (MEMS) variable capacitor. MEMS behavior in electrical circuits; Methods for circuit simulation; Applications on communication circuits.

Presents information on a study which proposed an approach for the analysis of the nonlinear behavior of analog integrated circuits. Description of nonlinearities; Calculation of nonlinear responses; Discussion on algorithmic aspects; Conclusions.

A correction to the article "A 70 dB DR 10 b 0-to-80 MS/s current-integrating SAR ADC with adaptive dynamic range" that was published in May, 2014.