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Your search keyword '"Zaid Ghanim"' showing total 2 results
Start Over Author "Zaid Ghanim" Topic integrated software
2 results on '"Zaid Ghanim"'

1. Scheduling lecturer system based on FPGA

Author

Zaid Ghanim Mohammed, Abdullah Mohammed Abdulallah Hamdoon, and Mothanna Sharaby Aziz

Subjects
Computer science, business.industry, Embedded system, VHDL, Integrated software, Spartan, User requirements document, Field-programmable gate array, business, computer, computer.programming_language, Scheduling (computing)
Abstract

The work is intended to automatically organize the lecture time length and break interval between lectures in schools. Its replaces manual organization and switching by automatic controlled system to perform the mission. The designed system determine accurately the scheduling time of the classes in the school according to the calendar. The system allows the user to reprogram the scheduling mode according to the user requirements. The system designed using VHDL language and configured on Spartan 3E FPGA slice using integrated software environments (ISE). The system performance is debugged using the tool kit with FPGA device.

Published
2018
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2. Design and implementation of single bit error correction linear block code system based on FPGA.

Author

Hamdoon, Abdullah Mohammed A., Mohammed, Zaid Ghanim, and Mohammed, Emad A.

Subjects
*BLOCK codes, *LINEAR codes, *ERROR correction (Information theory), *ERROR-correcting codes, *ERROR detection (Information theory), *HAMMING codes, *INTEGRATED software, *DEBUGGING
Abstract

Linear block code (LBC) is an error detection and correction code that is widely used in communication systems. In this paper a special type of LBC called Hamming code was implemented and debugged using FPGA kit with integrated software environments ISE for simulation and tests the results of the hardware system. The implemented system has the ability to correct single bit error and detect two bits error. The data segments length was considered to give high reliability to the system and make an aggregation between the speed of processing and the hardware ability to be implemented. An adaptive length of input data has been consider, up to 248 bits of information can be handled using Spartan 3E500 with 43% as a maximum slices utilization. Input/output data buses in FPGA have been customized to meet the requirements where 34% of input/output resources have been used as maximum ratio. The overall hardware design can be considerable to give an optimum hardware size for the suitable information rate. [ABSTRACT FROM AUTHOR]

Published
2019
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