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A low-power parasitic-insensitive switched-capacitor (SC) integrator is proposed for ΔΣ ADCs. Compared to the conventional SC integrator, the new one achieves much lower power dissipation for the same sampling noise specification. A cancellation technique is used to reduce the nonlinearity of the integrator. An effective ΔΣ ADC topology is described which can incorporate the new integrator. Simulation shows that high linearity can be achieved by the new integrator, while consuming very low power. [ABSTRACT FROM AUTHOR]

A charge compensation technique is proposed for switched capacitor stages with low-gain opamps. It cancels the error charge flow during the operation phase, thus enhancing the accuracy. A capacitive Tnetwork can be employed to implement the resulting large capacitor ratio. A switched-capacitor integrator and a sample-and-hold stage were designed and simulated to verify the proposed technique. [ABSTRACT FROM AUTHOR]

A high-precision switched-capacitor integrator using a low-gain opamp is proposed. The circuit contains a main signal path and a predictive signal path which makes the correlated double sampling more effective. The proposed integrator was simulated using SPICE parameters for a 180 nm CMOS process with a supply voltage of 1.2 V. The circuit exhibited much lower harmonic distortion than those described in earlier works. [ABSTRACT FROM AUTHOR]

A novel double-sampling integrator is proposed, which is insensitive to path mismatch, and does not require bilinear integration. It allows the use of efficient design methods for ΔΣ ADCs. [ABSTRACT FROM AUTHOR]