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The electrical characteristics of a V/p-GaN Schottky junction have been investigated by current-voltage (I-V) and capacitance-voltage (C-V) characteristics under the assumption of the thermionic emission (TE) theory in the temperature range of 120-280 K with steps of 40 K. The zero-bias barrier height (ΦB0), ideality factor (n), flat-band barrier height (ΦBF) and series resistance (RS) values were evaluated and were found to be strongly temperature dependent. The results revealed that the ΦB0 values increase, whereas n, ΦFB and RS values decrease, with increasing temperature. Using the conventional Richardson plot, the mean barrier height (0.39 eV) and Richardson constant (8.10 × 10−10 Acm−2 K−2) were attained. The barrier height inhomogeneities were demonstrated by assuming a Gaussian distribution function. The interface state density (NSS) values were found to decrease with increasing temperature. The reverse leakage current mechanism of the V/p-GaN Schottky junction was found to be governed by Poole-Frenkel emission at all temperatures. [ABSTRACT FROM AUTHOR]

The capacitance-frequency (C-f) and conductance-frequency (G-f) characteristics of the as-deposited and 400°C annealed Ni/n-GaP/Al diode were measured in a temperature range of 100-320 K with steps of 20 K. The values of interface state density Nss and their time constant were obtained from the temperature-dependent C-f and G-f characteristics in the measurement frequency range of 5.0 kHz to 5 MHz. The effect of annealing and measurement temperature on Nss and time constant of a Ni/n-GaP Schottky diode were analyzed from the forward bias voltage to the reverse bias voltage − 0.60 with steps of 0.30 V. The Nss value ranges from 8.8 × 1011 cm−2eV−1 at 0.60 V to 5.71 × 1011 cm−2eV−1 at − 0.60 V for the as-deposited diode, and 1.3 × 1012 cm−2eV−1 at 0.60 V to 5.5 × 1011 cm−2eV−1 at − 0.60 V for the 400°C annealed diode at a measurement temperature of 300 K. The interface state density value increases with high measurement temperature for the as-deposited and annealed diode. [ABSTRACT FROM AUTHOR]

Capacitance vs. voltage ( $$C{-}V$$ ) curves at AC high frequency of a metal-insulator-semiconductor (MIS) capacitor are investigated in this paper. Bi-dimensional simulations with Silvaco TCAD were carried out to study the effect of oxide thickness, the surface of the structure, frequency, temperature and fixed charge in the oxide on the $$C{-}V$$ curves. We evaluate also the analysis of MIS capacitor structures by different substrate doping concentrations with and without interface state density at different temperatures (100, 300 and 600 K). These studies indicate that the doping substrate concentration and the traps enormously affect the high-frequency $$C{-}V$$ curve behaviour. We also demonstrate that for low and high temperatures, the high-frequency $$C{-}V$$ curves behaviour changes, indicating that the capacitance due to the substrate is significantly influenced in these conditions (bias and substrate doping concentration). [ABSTRACT FROM AUTHOR]

The effects of rapid thermal annealing on the electrical and structural properties of a fabricated Au/Y/p-InP Schottky barrier diode (SBD) have been investigated. The estimated Schottky barrier heights (SBHs) of the as-deposited and 200 °C annealed Au/Y/p-InP SBDs are found to be 0.62 eV (I–V)/0.83 eV (C–V) and 0.63 eV (I–V)/0.92 eV (C–V) respectively. However, the SBH increases to 0.65 eV (I–V)/0.96 eV (C–V) upon annealing at 300 °C. Further, the SBH slightly decreases to 0.59 eV (I–V)/0.78 eV (C–V) for contact annealed at 400 °C. The SBH, ideality factor and series resistance of the Au/Y/p-InP SBD are estimated by Norde and Cheung's methods. Also, the discrepancy between SBHs estimated from I–V, C–V, Norde and Cheung's methods are described and discussed. It is noted that the interface state density of the Au/Y/p-InP SBD decreases upon annealing at 300 °C and then slightly increases after annealing at 400 °C. The AES and XRD measurements have revealed that the formation of Au–In, Au–P and Y–P interfacial phases at the interface may be the reason for the increase and decrease of SBHs upon annealing. The AFM results showed that the surface morphology of the Au/Y Schottky contact is fairly smooth at various annealing temperatures. [ABSTRACT FROM AUTHOR]

The effects of inserting a thin gold (Au) layer between the indium tin oxide (ITO) electrode and the poly [2-methoxy-5-(2-ethylhexyl-oxy)-p-phenylenevinylene] (MEH-PPV) organic material on the electrical and interface state properties of a ITO/MEH-PPV/Al device are investigated through current–voltage I ( V ), and capacitance–voltage characteristics C ( V ). The modified anode was characterized by atomic force microscope (AFM), and UV–vis transmittance spectra. The atomic force microscopy (AFM) surface roughness analysis indicates that a uniform and smoother surface is formed when the ITO is covered by the Au interlayer. A decrease in the transmittance and the optical band gap is observed in ITO/Au anode. The ITO/Au/MEH-PPV/Al device shows improved current density–voltage characteristics as compared with the ITO/MEH-PPV/Al. Diode parameters such as ideality factor, barrier height, series resistance and Shunt resistance are calculated using Schottky model corrected from the series and Shunt resistances. In the presence of the Au interlayer, the junction resistance across the ITO/MEH-PPV interface is significantly reduced, leading to an improvement in hole injection. The interface state density ( N ss ) values and the time constant of the interface states ( τ ) are obtained by the development of a new approach by the fit of the capacitance with three capacitances in series, according to Nicollian and Goetzberger formula. A decrease in the interface state density is observed when the Au interlayer is introduced at the ITO/organic layer interface. The main factors contributing to such improvements induced by the thin gold buffer layer are discussed. [ABSTRACT FROM AUTHOR]

The field-modulated surface photovoltage (SPV) method, a very surface sensitive technique, was utilized to determine electronic interface properties on wet-chemically oxidized and etched silicon (Si) interfaces. The influence of preparation-induced surface micro-roughness and un-stoichiometric oxides on the resulting the surface charge, energetic distribution Dit(E), and density Dit,min of rechargeable states was studied by simultaneous, spectroscopic ellipsometry (SE) measurements on polished Si(111) and Si(100) substrates. Based on previous findings and new research, a study of conventional and newly developed wet-chemical oxidation methods was established, correlating the interactions between involved oxidizing and etching solutions and the initial substrate morphology to the final surface conditioning. It is shown, which sequences of wet-chemical oxidation and oxide removal, have to be combined in order to achieve atomically smooth, hydrogen terminated surfaces, as well as ultra-thin oxide layers with low densities of rechargeable states on flat, saw damage etched, and textured Si substrates, as commonly applied in silicon device and solar cell manufacturing. These conventional strategies for wet-chemical pre-treatment are mainly based on concentrated solutions. Therefore, special attention was put on the development of more environmentally acceptable processes, utilizing e.g. hot pure water with low contents of oxygen or hydrochloric acid, and of ozone, working at ambient temperatures. According to our results, these methods could be a high quality and low cost alternative to current approaches with liquid chemicals for the preparation of hydrophobic Si substrate surfaces and ultra-thin passivating oxide layers. As demonstrated for selected examples, the effect of optimized wet-chemical pre-treatments can be preserved during subsequent soft plasma enhanced chemical vapor depositions of Si oxides (SiOx), or amorphous materials such as Si (a-Si:H), Si nitride (a-SiNx:H), AlOx/a-SiNx and Si carbide (a-SiC:H) and enhance the energy conversion efficiency of heterojunction silicon solar cells. [ABSTRACT FROM AUTHOR]

Abstract: The impact of the post thermal oxidation of the Al2O3/Ge structures on metal-oxide-semiconductor interface properties has been systematically investigated. Also, the reaction mechanisms at the Al2O3/Ge interfaces with thermal oxidation through the thin Al2O3 layer have been investigated. Interface state density around the midgap of Ge is reduced with the formation of AlGeO layer near the Al2O3/Ge interface. Also, through the detail analysis of chemical bonding state of Ge oxide, it is found that the AlGeO layer which has a stable phase, in other words Al6Ge2O13, is formed near the Al2O3/Ge interface, and a GeO2 layer is formed on the Al2O3 surface, suggesting Ge or GeO diffusion from the Ge surface. Furthermore, it is clarified that the mechanism of formation of AlGeO layer is different from that of GeO2 on the Al2O3 surface which is limited by oxygen diffusion in Al2O3 layer. Therefore, Al6Ge2O13 formation near the Al2O3/Ge interface without the GeO2 formation on the Al2O3 surface is a key to achieve a low interface state density and a thin equivalent SiO2 thickness. [Copyright &y& Elsevier]

Highlights: [•] Cr/n-Si Schottky Schottky barrier diodes were prepared by the electrodepositing method. [•] The electrical characteristics of the Cr/n-Si Schottky barrier diode were investigated. [•] The interface state density of the diode has an exponential rise. [•] The main parameters were calculated using different methods. [Copyright &y& Elsevier]

Highlights: [•] Ge gate stacks by exposing oxygen plasma to ALD Al2O3/Ge were proposed. [•] GeO x formed between Al2O3 and Ge significantly reduces interface state density. [•] High electron mobility of 690cm2/Vs in Ge nMOSFETs with EOT of 0.7–0.8nm. [•] High hole mobility of 546cm2/Vs in Ge p-MOSFETs with EOT of 0.7–0.8nm. [Copyright &y& Elsevier]

Highlights: [•] The energy distribution of electrically active interface states at the Al2O3/In0.53Ga0.47As interface has been evaluated. [•] Analysis reveals a peak of donor-like interface trap density 1.5×1013 cm−2 eV−1 located at ∼0.36eV above E v. [•] Acceptor-like interface traps are also present located in the In0.53Ga0.47As conduction band. [•] The interface state distribution is similar to reports for others oxides. [•] Results suggest the interface states originate from the In0.53Ga0.47As surface. [Copyright &y& Elsevier]

Highlights: [•] The junction of Au/AlPcCl/PTCDI/ITO exhibit rectifying characteristic showing a p–n diode like behavior. [•] High photosensitivity for the device is observed. [•] The device shows an improvement in photovoltaic parameters. [•] The interface states density is not effective on the device performance characteristics under high frequency. [Copyright &y& Elsevier]

We have reported a detailed investigation of frequency dependent properties of the Au/perylene-monoimide (PMI)/n-Si Schottky diodes in this study. Schottky diodes based on PMI have been fabricated by spin coating method. The capacitance–voltage (C–V) and conductance–voltage (G–V) characteristics have been measured in the frequency range from 30kHz to 1MHz at room temperature. The values of measured capacitance and conductance under both reverse and forward bias have been corrected for the effect of series resistance to obtain the real diode capacitance and the conductance values. The density of interface states ( ) distribution profiles as a function of frequency has been extracted from the corrected C–V and G–V measurements. Interface trap states of the PMI/n-Si Schottky device have decreased by increasing the applied frequency and were found to be 8.13×1011 and 1.75×1011 eV−1 cm−2 for 30kHz and 1MHz, respectively. [ABSTRACT FROM AUTHOR]

Abstract: Fabrication of bonded Germanium on insulator (GeOI) substrates with thin Al2O3/SiO2 buried oxide layers was demonstrated for the first time. Thin Al2O3 layers grown by an atomic-layer deposition method, which have hydroxyl groups on their surfaces, were inserted to Ge/SiO2 interfaces to strengthen the adhesion between them. The interface bonded in the atmosphere at room temperature without post-anneal processes is flat and exhibits no additional interface. After the wafer bonding, thick GeOI layers were thinned by mechanical polishing, chemical mechanical polishing and O3 water etching. The flatness of the surface is equivalent to that of commercially available Ge substrates. The interface state density (D it) of the Ge/Al2O3 interface is estimated with low-temperature conductance technique and the D it of as low as 3.9×1011 eV−1 cm−2 at the interface is obtained. This value is almost one order of magnitude lower than previously reported D it of Ge/SiO2 interfaces. These results suggest that negligible negative impact on carrier mobility and sub-threshold characteristics is expected for the back-side interface in the GeOI substrate with thin Al2O3/SiO2 BOX layers. [Copyright &y& Elsevier]

Abstract: Effect of W and TiN/W gate metal on the interface quality of La2O3/InGaAs metal–oxide-semiconductor (MOS) interface is investigated. Hard X-ray photoelectron spectroscopy revealed that gate metal greatly affects the oxidation states at La2O3/InGaAs interface after post-metallization annealing (PMA). Results demonstrate that TiN/W gate metal can effectively control the reaction at La2O3/InGaAs interface and also suppress the formation of As, Ga, and In oxides. As a result, superior capacitance–voltage (C–V) characteristics with low interface state density (D it) of 4.6×1011 cm−2/eV (∼0.1eV from midgap) and leakage current below 10−5 A/cm2 was obtained for TiN/W/La2O3 (10nm)/InGaAs MOS capacitors. The MOS structure integrity was preserved for annealing temperature up to 620°C. [Copyright &y& Elsevier]

Abstract: The electrical properties of an Al2O3/Ge gate stack structure were improved by O2-annealing. The interface state density can be decreased by O2-annealing without the formation of a GeO2 interfacial layer. X-ray photoelectron spectroscopy measurements revealed that Ge diffusion into the Al2O3 layer occurs and Ge is uniformly distributed in the oxide layer after O2-annealing. Crystallization of the Al2O3 film was observed after O2-annealing at 550 °C and was identified as an Al–Ge–O compound using cross sectional transmission electron microscopy and transmission electron diffraction measurement. [Copyright &y& Elsevier]

Abstract: The effects of controlling InGaAs substrate temperature during electron beam deposition of HfO2 on electrical characteristics of W/HfO2/n-In0.53Ga0.47As capacitors are investigated. It is found that by depositing a thin HfO2 layer at the interface when substrate temperature is raised to 300°C, frequency dispersion at depletion and accumulation conditions is reduced and interface state density is lowered regardless of the HfO2 thickness. Cross-sectional transmission electron microscopy images have revealed that the formation of mesoscopic voids in the InGaAs substrate near the interface is suppressed with HfO2deposition at 300°C at the interface. A band diagram with an additional bulk trap energy level has been proposed to explain the frequency dispersion and conductance peaks at accumulation condition. [Copyright &y& Elsevier]

Abstract: Thin film of poly(3-octylthiophene) (P3OT) was successfully prepared using dip coating technique. The morphology and the crystal structure of the prepared thin film were characterized by scanning electron microscopy (SEM) and X-ray diffraction (XRD), respectively. A study on interface states density distribution and characteristic parameters of the Al/P3OT/ITO device capacitor have been made. The diode parameters such as ideality factor, series resistance and barrier height were extracted from the forward biasing J–V characteristics. The energy distribution of the interface state density D it was determined from the forward bias J–V characteristics by taking into account the bias dependence of the effective barrier height. The C–V and G/ω–V characteristics were measured in the frequency range from 10kHz to 1MHz and dc biasing voltage swept from −4V to +4V at room temperature (300K). The non-ideal behavior of J–V and C–V characteristics can be attributed to the presence of the interface and the series resistance. [Copyright &y& Elsevier]

Abstract: We have demonstrated the control of interfacial properties of Pr-oxide/Ge gate stack structure by the introduction of nitrogen. From C–V characteristics of Al/Pr-oxide/Ge3N4/Ge MOS capacitors, the interface state density decreases without the change of the accumulation capacitance after annealing. The TEM and TED measurements reveal that the crystallization of Pr-oxide is enhanced with annealing and the columnar structure of cubic-Pr2O3 is formed after annealing. From the depth profiles measured using XPS with Ar sputtering for the Pr-oxide/Ge3N4/Ge stack structure, the increase in the Ge component is not observed in a Pr-oxide film and near the interface between a Pr-oxide film and a Ge substrate. In addition, the N component segregates near the interface region, amorphous Pr-oxynitride (PrON) is formed at the interface. As a result, Pr-oxide/PrON/Ge stacked structure without the Ge-oxynitride interlayer is formed. [Copyright &y& Elsevier]

We report the demonstration of novel techniques for surface passivation of gallium nitride (GaN), comprising the steps of in situ vacuum anneal (VA) and silane–ammonia (\SiH4 + \NH3) or silane (\SiH4) treatment for GaN, prior to the formation of high-permittivity gate dielectric in a multichamber metal–organic chemical vapor deposition tool. The effects of VA temperature and the \SiH4 + \NH3 or \SiH4 treatment temperature on interface quality was investigated. High-temperature capacitance–voltage characterization was also performed to probe the interface states near the midgap of GaN. Interface state density Dit as a function of energy was extracted. Without in situ passivation, a control TaN/HfAlO/GaN capacitor has a midgap Dit of \sim\!\2.0 \times \10^12\ \cm^-2 \cdot \eV^-1. This is reduced to \sim\!\4.0 \times \10^11\ \cm^-2 \cdot \eV^-1 and \sim\! \2.0 \times \10^10\ \cm^-2 \cdot \eV^-1 for samples that received the in situ \SiH4 + \NH3 treatment and in situ \SiH4 treatment, respectively. [ABSTRACT FROM AUTHOR]

Abstract: TiO2 thin films were deposited on polycrystalline n-type Si substrate using DC magnetron sputtering system. To improve the crystal quality, thermal annealing (TA) process was done at 700°C and 900°C. The effect of TA on the structural properties was investigated using high resolution X-ray diffraction (HRXRD). It was observed that the phase transition from amorphous phase to anatase and rutile phases occurs at 700°C and 900°C, respectively. Au/TiO2/n-Si structures were also fabricated for the investigation of TA on the main electrical parameters, such as ideality factor (n), barrier height (Φ B), series resistance (R s), shunt resistance (R sh) and interface states (N ss). The current–voltage (I–V) and capacitance–voltage (C–V) characteristics have been investigated at room temperature and results have been compared with each other. The electrical characteristics showed that TA strongly affects the main electrical parameters. The rectifying ratio of Au/n-Si structures with anatase phase TiO2 was to be 140 while the rutile phase was to be 8864. The leakage current was also found to be very sensitive to the annealing temperature, and also the magnitude of the leakage current for rutile phase is 15 times lower than the anatase phase''s. In addition, the energy distribution profile of N ss of the structures was obtained from the forward bias I–V data by taking the bias dependence of the effective barrier height (Φ e) into account. For both of the samples, the value of N ss decreases with TA. Similarly, the values of R s and R sh of the structures obtained from the forward bias I–V data were found as 209Ω and 42kΩ for the anatase and 59Ω and 598kΩ for the rutile phase. These results show that the performance of the Au/TiO2/n-Si structure improved with thermal annealing. [Copyright &y& Elsevier]

Abstract: We have fabricated a poly(aniline-3-methyl thiophene) organic thin material on p-Si substrate by placing a solution of copolymer in acetonitrile on top of a p-Si substrate and then evaporating the solvent. The electrical and interface state density properties of the poly(aniline-3-methyl thiophene) copolymer/p-Si/Al diode have been investigated through methods using current–voltage (I – V), Cheung''s, and a modified Norde''s function. Good agreement was observed with the values of barrier height as obtained from all of these methods. The diode shows a non-ideal I – V behavior with an ideality factor greater than unity, which could be ascribed to the interfacial layer, interface states and series resistance. The interface state density of diode was determined using the forward-bias I – V characteristic technique at room temperature, and it decreases exponentially with bias from 1.39×1016 cm− 2 eV− 1 in (0.06− E v) eV to 4.86×1015 cm− 2 eV− 1 in (0.51− E v) eV. [Copyright &y& Elsevier]

Abstract: 4H-SiC–oxide interfaces formed by various oxidation methods on SiC (0001) Si- and () C-face substrates have been characterized by performing spectroscopic ellipsometry in wide spectral region including deep UV spectral range and capacitance–voltage measurements. The results exhibit that the refractive indices of the interface layers well correlate with interface state density in all the cases of oxidation processes. To investigate the difference in interface characteristics between wet and dry oxidation, we compared to the sample fabricated by wet oxidation followed by heating in Ar or O2 atmosphere, aiming to remove hydrogen related species at the interface. We also tried to make clear the difference in the interface characteristics between Si- and C-faces by lowering the oxidation rate of C-face down to those for Si-face. Putting together with all of the results obtained, we discuss the origins that determine the interface characteristics in terms of both the optical and electrical characterizations. [Copyright &y& Elsevier]

Abstract: The gate and subthreshold drain leakage currents are investigated experimentally in triple-gate FinFETs for power supply voltage V dd =1V. The gate and drain leakage currents are analyzed in terms of the fin width and gate length to clarify their origin. In wide FinFETs, the measured subthreshold drain current is much larger than the gate tunneling current due to the short-channel effects. In narrow FinFETs with negligible short-channel effects, the importance of the trap-assisted sidewall-gate edge tunneling current on the drain leakage current has been demonstrated. This leakage current behavior with decreasing the fin width has been attributed to the higher sidewall-gate interface trap density compared to the top-gate interface trap density. [Copyright &y& Elsevier]

MgO and Sc2O3 were deposited by gas source molecular beam epitaxy on GaN. MgO was found to produce lower interface state densities than Sc2O3, 2–3 × 1011 vs. 9–11 × 1011 eV−1 cm−2. The good electrical quality of the interface is believed to be due to the presence of a single crystal epitaxial layer at the GaN surface. By contrast, the MgO was found to be more sensitive to environmental and thermal degradation than the Sc2O3. The environmental degradation is believed to be due to interaction with water vapor in the air and was suppressed by capping of the MgO. Annealing at the temperatures needed for implant activation in GaN produced significant roughening of the MgO/GaN interface and an order of magnitude increase in the interface state density. This sensitivity to thermal degradation will require changes in the processing sequence presently envisioned for e-mode devices in order to avoid damaging the interface and increasing the gate leakage in the device. [Copyright &y& Elsevier]

The vapor cooling condensation system was designed and used to deposit homostructured ZnO-based metal-oxide-semiconductor field-effect transistors (MOSFETs) on sapphire substrates. Owing to the high quality of the deposited, various ZnO films and interfaces, the resulting MOSFETs manifested attractive characteristics, such as the low gate leakage current of 24 nA, the low average interface state density of 2.92 × 10 11 cm −2 eV −1 , and the complete pinch-off performance. The saturation drain–source current, the maximum transconductance, and the gate voltage swing of the resulting homostructured ZnO-based MOSFETs were 5.64 mA/mm, 1.31 mS/mm, and 3.2 V, respectively. [ABSTRACT FROM AUTHOR]

Electrical interface quality of various high-k dielectrics on GaSb, including Al2O3, HfO2, LaAlO3, GdScO3, and HfO2/Ga2O3 bilayer has been studied and compared with reference low (AlGaSb) and high Dit (native oxide) interfaces using photoluminescence intensity measurements for the first time. Al2O3 and HfO2/Ga2O3 bilayer dielectrics are identified with the lowest interface recombination velocity (S=7\times 10^4~cm/s) and consequently Dit integrated across essentially the entire bandgap. However, S for even the best identified high-k dielectrics is elevated by 140\times over the low Dit AlGaSb reference indicating the need of further improvements for envisioned use in Sb based MOSFETs. [ABSTRACT FROM AUTHOR]

Highlights: [•] Gate electrode metals have impacts on gate dielectrics and interface properties. [•] MOS capacitors with Pd gate electrode can provide thinnest CET. [•] Pd gate electrode provides better MOS interface properties in HfO2/InGaAs. [Copyright &y& Elsevier]

Abstract: In this work we have compared the SiO2/SiC interface electrical characteristics for three different oxidations processes (dry oxygen, water-containing oxygen and water-containing nitrogen atmospheres). MOS structures were fabricated on 8° off-axis 4H-SiC(0001) n- and p-type epi-wafers. Electrical characteristics were obtained by I–V measurements, high-frequency capacitance–voltage (C–V) and ac conductance (G–ω) methods. Comparing the results, one observes remarkable differences between samples which underwent different oxidation routes. Among the MOS structures analyzed, the sample which underwent wet oxidation with oxygen as carrier gas presented the higher dielectric strength and lower values of interface states density. [Copyright &y& Elsevier]

Abstract: SiO2/Si structure has been prepared by atmospheric-pressure (AP) plasma oxidation at 400°C using gas mixtures of 0.5–5% O2 and He. From the characterization results of thickness, refractive index, atomic composition and electrical properties of the oxide films, it is found that the properties of SiO2/Si structures formed by AP-plasma oxidation are similar to those of high-temperature grown thermal oxides. By optimizing formation conditions, the SiO2/Si structure with a low interface state density of 1.4×1010 cm−2 eV−1 is obtained. On the other hand, the positive fixed charge density in the AP-plasma oxide film is relatively high at 5.3×1011 cm−2. These characteristics (low interface state density and high fixed charge density) are useful for effective field-effect passivation of Si surfaces for photovoltaic application. [Copyright &y& Elsevier]

Abstract: Formation processes of Ge3N4 by radical nitridation and electrical properties of Pr-oxide/Ge3N4/Ge structure were investigated. Stoichiometric Ge3N4 is successfully formed by the radical nitridation at temperatures from 50 to 600°C. Change in the nitridation temperature dependence of the saturated thickness of the Ge3N4 suggests different dominant diffusion species. Leakage current density through the Ge3N4 is minimized at a nitridation temperature of 300°C. The XPS analyses of the Pr-oxide/Ge3N4/Ge suggest decomposition of Ge3N4 during atomic layer deposition of the Pr-oxide and formation of Pr-oxynitride at the Pr-oxide/Ge interface. An interface state density in the Al/Pr-oxide/Ge3N4/Ge capacitor is drastically reduced by forming gas annealing. [Copyright &y& Elsevier]