1. Layout dependency of PMOS off current degradation due to off-state stress
- Author
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Hong Sik Park, Jae Yong Seo, Won Shik Lee, Gu Gwan Kang, Tae hun Kang, Sabina Lee, and Byung Heon Kwak
- Subjects
Materials science ,business.industry ,Gate oxide ,Logic gate ,Electrical engineering ,Optoelectronics ,Inverter ,Nitride ,business ,Quantum tunnelling ,PMOS logic ,Voltage ,Leakage (electronics) - Abstract
The paper presents layout dependency of PMOS I off degradation during off-state stress, which is induced by inverter leakage currents (I off ) have been increased by electron trapping in PMOSFET. Extensive test result represents time dependence of PMOS hump is based on the STI edge trap. To conclude, we can expect that hot temperature bake evaluation causing partial recovery of I off leakage is the reason for that trap location is a nitride liner of STI edge rather than edge gate oxide.
- Published
- 2009
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