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Multiphase drives (MPD) in general and six-phase in particular have been gaining popularity in many industries, which calls for a proper multiphase inverter (MPI) design. For voltage source inverter (VSI)-fed drives, the knowledge of voltage and current stresses on the dc-link are imperative for input capacitor sizing. To this end, the voltage and current stresses on the dc-link capacitor in two-level six-phase VSIs are examined thoroughly in this article for two configurations of load/winding spatial distribution: symmetric and asymmetric. First, the harmonic spectrum of the input dc current of each inverter is analyzed in detail by benchmarking them against the conventional three-phase VSI, to precisely establish the dc-capacitor requirement reduction in six-phase counterparts. Second, analytical formulae for the dc-link capacitor voltage ripples are derived for both configurations. Third, simple formulae for dc-capacitor sizing for six-phase VSIs with different load configurations are provided. The accuracy of the derived formulae is verified by simulation and experimental testing at various power factors and modulation depth. It is found that six-phase VSI supplying symmetric and asymmetric loads reaps 10% and 7% lower dc-link current ripples, respectively. Hence, six-phase symmetric loads yield the smallest capacitor size. [ABSTRACT FROM AUTHOR]

High-power boost converters offer significant benefits to hybrid and electric vehicles, because higher-voltage propulsion power equates to lower motor losses. However, the converters themselves must have high efficiency and high power density in order to make the system-level trade-off beneficial. Thus, this paper presents an optimized design process of high power multi-phase interleaved bidirectional boost converters. In order to achieve a fast and accurate analysis and design, a generalized method is developed for the calculations of required phase inductance and output capacitance. In addition, a genetic algorithm (GA) optimization method is implemented for the inductor design. Using the proposed design process, a 3-phase 60 kW interleaved converter is designed and tested using paralleled SiC MOSFETS. The converter achieves peak efficiency of 99.2% at 10 kW and is $>$ 98% efficiency from 5% to 100% load. The resulting power density is 9.4 kW/L, which can be further improved to 12.2 kW/L with alternate terminal connectors. [ABSTRACT FROM AUTHOR]

This paper presents a novel fault-tolerant method for active–neutral-point-clamped (ANPC) inverter using a modified carrier-based pulsewidth modulation. At a fault event, the ANPC inverter is divided into subinverters, and the modulating signal is modified to two modulating signals. The modified modulating signals are used to control the subinverters and allow continuous operation of the three-level ANPC inverter during faulty conditions even up to four open-switch faults per phase. This technique provides the fault-tolerant capability of the ANPC inverter without the need to add any additional phase legs or complex control strategies. Furthermore, the proposed technique ensures the voltage balancing of the dc-link capacitors. The performance of the proposed fault-tolerant technique is verified through simulation studies in MATLAB/Simulink under different faulty conditions. The feasibility of the proposed technique is also verified experimentally. [ABSTRACT FROM AUTHOR]