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This paper presents the first low-complexity realization of an LDPC-code sparse code multiple access (SCMA) receiver with a high-throughput LDPC decoder and a multi-mode SCMA detector. The minimum mean-square error with parallel interference cancellation (MMSE-PIC) algorithm is adopted in the SCMA detection. The modified user-node operations in the MMSE-PIC-based message-passing detector improve the convergence rate in error performance. The proposed receiver also supports multi-user iterative detection and decoding (MU-IDD) to improve the error rate performance. The proposed receiver supports both $4\times 6$ and $8\times 12$ SCMA systems. The proposed MU LDPC decoder has a 57.1% lower hardware complexity than the direct-mapped design that is achieved through hardware sharing and memory access scheduling. Designed in a 40-nm CMOS technology, the SCMA receiver integrates 10.9M logic gates in an area of $3.382\times 3.382$ mm2. The proposed design achieves a gross throughput of 1.198 Gb/s and 599 Mb/s for $8\times 12$ and $4\times 6$ SCMA systems, respectively, under a practical situation. It dissipates 813 mW at a clock frequency of 300 MHz from a 0.9-V supply. [ABSTRACT FROM AUTHOR]

For high-rate low-density parity-check (LDPC) codes, layered decoding processing can be reordered such that the first-in-first-out (FIFO) buffer that stores variable-to-check (V2C) messages is not needed and, hence, the memory area can be minimized, but at the cost of increased data dependency. This paper presents three techniques that can be used to implement an efficient reordered layered decoder. First, with the assistance of a graph coloring method, the required minimum number of V2C sign memory banks can be theoretically determined, with the corresponding pipeline architecture also designed. After that, the integer linear programming technique is adopted so as to arrange the V2C sign memory banks in a manner that minimizes the number of pipeline stalls, thereby increasing throughput. In order to further simplify the decoder, the first minimum values are not stored if the proposed modified min-sum algorithm is used. The proposed techniques are demonstrated by implementing a rate-0.905 (18396,16644) QC-LDPC decoder using 90-nm CMOS technology. When using the proposed techniques, implementation results show that the throughput-to-area ratio (TAR) increases by 58.9% without sacrificing error-rate performance. [ABSTRACT FROM PUBLISHER]

This paper presents a high-throughput, area-efficient and energy-efficient iterative detection and decoding (IDD) receiver for low-density parity-check (LDPC)-coded multiple-input multiple-output (MIMO) systems. A layered non-resetting IDD technique is used to minimize the number of inner iterations for a required error performance. An area-efficient minimum mean-square error with parallel interference cancellation (MMSE-PIC) detector is devised to simplify matrix inversion. A detector-decoder interface that is used to exchange soft messages efficiently is proposed. Given the throughput specifications, inner and outer loops are optimally combined to maximize the error performance. The design specifications defined in the IEEE 802.11n standard are adopted as the design target. A 4 \times 4 antenna configuration with BPSK, QPSK, 16-QAM modulations are realized in silicon. The designs that support 64-QAM and 256-QAM modulations are also demonstrated for comparison with prior work. Fabricated in 40 nm technology, the chip integrates 998k logic gates in 1.33 mm^2 and achieves a maximum throughput of 794 Mb/s. The chip dissipates 135 mW at 0.9 V, achieving an energy efficiency of 170 pJ/bit. [ABSTRACT FROM AUTHOR]

For an efficient multimode low-density parity-check (LDPC) decoder, most hardware resources, such as permutators, should be shared among different modes. Although an LDPC code constructed based on a Reed–Solomon (RS) code with two information symbols is not quasi-cyclic, in this paper, we reveal that the structural properties inherent in its parity-check matrix can be adopted in the design of configurable permutators. A partially parallel architecture combined with the proposed permutators is used to mitigate the increase in implementation complexity for the multimode function. The high check-node degree of a high-rate RS-LDPC code leads to challenges in the efficient implementation of a high-throughput decoder. To overcome this difficulty, the variable nodes have been partitioned into several groups, and each group is processed sequentially in order to shorten the critical-path delay and hence increase the maximum operating frequency. In addition, shuffled message-passing decoding is adopted, since fewer iterations can be used to achieve the desired bit-error-rate performance. In order to demonstrate the usefulness of the proposed flexible-permutator-based architecture, one single-mode rate-0.84 decoder and two multimode decoders whose code rates range between 0.79 and 0.93 have been implemented. These decoders can achieve multigigabit-per-second throughput. Using the proposed architecture to support lower rate RS-LDPC codes, e.g., rate-0.568 code, is also investigated. [ABSTRACT FROM PUBLISHER]