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A distributed DLL (DDLL) with low jitter and high phase accuracy is proposed for the multiphase clock generator. The high-speed multiphase clock generator produces a five-phase clock at a frequency range of 8 to 10 GHz. Additionally, the discrete-time model for the distributed DLL and the analysis about stability and noise are proposed in this work. The measured rms jitter is 293.3 fs and the maximum phase mismatch is 1.4 ps. The proposed architecture can suppress the jitter by 58%. The distributed DLL occupies 0.03 mm2 active area in a 90-nm CMOS technology and consumes 15 mA from a 1.0-V supply.

As the data rate increases above Gb/s, the design of a clock and data recovery (CDR) circuit becomes a great challenge. A 3.125-Gb/s CDR is proposed to shorten the frequency acquisition time by employing a wide-linear-range frequency detector. Fabricated in a 0.18-mum 1P6M CMOS technology, the output jitter of this proposed CDR is measured as 70 ps (peak-to-peak) and 8.3 ps (rms). The measured bit-error rate (BER) is less than 10-12 for 231-1 PRBS. The proposed CDR occupies a chip area of 0.61 mm times 0.61 mm and dissipates 61 mW from a single 1.8-V power supply.

A low-jitter distributed DLL for multiple-phase clock generation is proposed. The distributed DLL monitors the phase difference for each output clock and the reference clock. This distributed DLL is fabricated in a 90 nm CMOS process and consumes 15 mW from a 1 V supply excluding output buffers. The distributed DLL operates from 8 to 10 GHz, which is consistent with the simulation results and also the fastest in CMOS technology.

A multiplying-DLL based frequency synthesizer with a fully-integrated loop capacitor employs an adaptive current adjusting loop to generate a low-jitter clock for LCD panel applications. The measured RMS jitter is 3.5 ps for 229.5-MHz output clock. The frequency synthesizer occupies 0.09 mm2 active area in a 0.18-mum CMOS technology and consumes 9 mW from a 1.8-V supply.