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A high-throughput 4 $\boldsymbol{\times }$ 4-bit multiplier was demonstrated using an extremely careful timing design for low-voltage rapid single-flux-quantum (LV-RSFQ) logic. The design considers the lengths of all wires, bias dependency of the delays, and load dependency of the signal splitters. The key is to intentionally use both Josephson transmission lines and passive transmission lines for gate-to-gate wiring, even over short distances, to form the same structure wiring as the clock lines. The structure of the multiplier is based on a bit-parallel, gate-level pipeline to exploit throughput. The test chip was fabricated using the AIST 10-kA/cm $\boldsymbol{^2}$ , Nb/AlOx/Nb, 9-Nb-layer Advanced Process 2. The measured maximum operating frequency, throughput, and power consumption without cooling cost in the high-speed on-chip test were 52 GHz, 52 G-operations per second (GOPS), and 134 $\boldsymbol{\mu }$ W, respectively. Although the switching speed of the Josephson junctions was reduced by 40 $\boldsymbol{\%}$ owing to the low-voltage operation, the obtained clock frequency was as high as that demonstrated with the standard bias voltage. The energy efficiency was 381 tera-operations per second per watt (TOPS/W) at 4.2 K. Further improvement in energy efficiency is expected by using low-voltage half-flux-quantum (LV-HFQ) circuits and shrinking the size of Josephson junctions.

Each superconductor logic family has distinct features and advantages. For instance, adiabatic quantum-flux-parametron (AQFP) circuits operate with very high energy efficiency, and rapid single-flux-quantum (RSFQ) circuits operate at very high clock frequencies. To build a hybrid system that combines the above advantages, we propose a compact interface between AQFP and RSFQ circuits that converts current signals in AQFP logic into flux signals in RSFQ logic using a non-adiabatic quantum-flux-parametron gate. Compared to a previously proposed AQFP/RSFQ interface, the proposed interface has far fewer Josephson junctions (4 vs. 11). We optimize the circuit parameters of the AQFP/RSFQ interface and demonstrate the interface at low speed as proof of concept. Furthermore, we demonstrate data propagation between AQFP circuits along a long passive transmission line via the AQFP/RSFQ interface at low speed to show that the AQFP/RSFQ interface can alleviate the interconnect length limit in AQFP circuits.

We demonstrated interface circuits between a half-flux-quantum (HFQ) circuit and a rapid single-flux-quantum (RSFQ) circuit to obtain SFQ/HFQ and HFQ/SFQ converters. These converters were created by simply inserting a resistor between an RSFQ circuit and the adjacent HFQ circuit, where both circuits are based on pulse logic. These converters enable us to create combinatory circuits that make the best use of the features of the two circuits. Using a DC/SFQ, SFQ/HFQ, HFQ/SFQ, and SFQ/DC converter, we measure an HFQ Josephson transmission line (JTL) composed of eight 0-0-π superconducting quantum interference devices (SQUIDs), which are the essential elements of an HFQ circuit. The 0-0-π SQUIDs are composed of two conventional Josephson junctions and a π-shifted ferromagnetic junction. The HFQ JTL demonstrated in this study is driven by a bias current 11-fold lower than that of a similar RSFQ JTL. These experimental results indicate that the HFQ circuit requires power that is two or more orders of magnitude lower than that of an RSFQ circuit.

Rapid single-flux quantum (RSFQ) circuits have recently attracted considerable attention as a promising cryogenic beyond CMOS technology for exascale computing. Energy-efficient RSFQ (ERSFQ) is an energy-efficient, inductive bias scheme for RSFQ circuits, where the power dissipation is drastically lowered by eliminating the bias resistors, while the cell library remains unchanged. An ERSFQ bias scheme requires the introduction of multiple circuit elements—current limiting Josephson junctions, bias inductors, and feeding Josephson transmission lines (FJTLs). In this article, parameter guidelines and design techniques for ERSFQ circuits are presented. The proposed guidelines enable more robust circuits resistant to severe variations in supplied bias currents. Trends are considered, and advantageous tradeoffs are discussed for the different components within a bias network. The guidelines provide a means to decrease the size of an FJTL and, thereby, reduce the physical area, power dissipation, and overall bias currents, supporting further increases in circuit complexity. A distributed approach to ERSFQ FJTL is also presented to simplify placement and minimize the effects of the parasitic inductance of the bias lines. This methodology and related circuit techniques are applicable to automating the synthesis of bias networks to enable large-scale ERSFQ circuits.

In recent years, rapid single flux quantum (RSFQ) circuits, which are promising for the development of high-speed digital electronics, have attracted widespread interest. Niobium nitride (NbN) films have also attracted significant attention for high-frequency applications in superconducting electronics because of their superior material parameters, including their high critical temperature T c and large gap voltage V g. To enable the development of all-NbN SFQ circuits, we have developed a fabrication process based on NbN junctions and inductors made of NbN strip lines. It is important to evaluate the inductance because it can affect the performance of an RSFQ circuit and is essential for the RSFQ design. We measured the inductance properties of both epitaxial and polycrystalline NbN strip lines using a superconducting quantum interference device modulation technique at 4.2 K and obtained the width dependence on the inductance of the NbN films. The penetration depth was then calculated from these measurements. The NbN inductance values were calculated numerically with respect to the penetration depth and were then compared with the measured values from the experiments. It was demonstrated that the differences between these values were within 5%. The results reported here will be useful for the design and fabrication of all-NbN RSFQ circuits.

Devices used for rapid single flux quantum (RSFQ) cell interconnects include passive transmission lines (PTLs) and Josephson transmission lines. In this article, we demonstrate software analysis methods with which reflections on PTLs can be improved through impedance matching without compromising the margins of the connected RSFQ logic cells. RSFQ cells are typically designed to connect to PTL transmitters and receivers before attaching the PTL interconnects. These transmitters and receivers are used as matching and buffer stages between the cell and the PTL; and can be adjusted to minimize impedance mismatching. We integrate PTL transmitters and receivers within the RSFQ cell to decrease the amount of Josephson junctions required to incorporate PTL interconnect functionality. Frequency domain analysis on each cell provides equivalent impedance characteristics used for impedance matching.

With the development of rapid single-flux-quantum (RSFQ) circuits, signal integrity issues of interconnects, such as signal distortion and crosstalk, become critical. Josephson junctions, as driver and receiver of interconnects, also affect signal integrity. Hence, it is significant to coanalyze time-domain responses of multicoupled passive transmission lines (PTLs) and Josephson junctions in RSFQ circuits. In this article, an accurate numerical method based on finite-difference time-domain (FDTD) is proposed to coanalyze multicoupled PTLs and Josephson junctions. The FDTD method is used to solve the telegraph equations of PTLs, and an iteration algorithm based on the contractive mapping theorem is proposed to solve the nonlinear equations generated by the Josephson junctions. In addition, the existence and uniqueness conditions of the nonlinear equations are also provided. The numerical and simulation results show that the proposed coanalysis method has the same accuracy as but higher efficiency than WRspice.

Energy-efficient rapid single flux quantum circuits having zero static power dissipation require a feeding Josephson junction transmission line (FJTL) to stabilize the power bus voltage. It is shown how a FJTL can be configured to obtain a desired current-bias window of constant delay, while preserving operability above and below that range as well, as a tradeoff against power and area. A test chip to validate circuit simulation results is designed with a gridded fabric for power delivery and cell placement, with consideration of passive transmission lines, magnetic flux exclusion, power bus isolation, and thermal noise. Measurements made on hardware fabricated in MIT Lincoln Lab's advanced 8-Nb-layer process correlate well with the model and indicate specific FJTL design challenges that need to be addressed.

Superconducting single flux quantum (SFQ) circuits have been shown to offer huge advantages that are ideal for high performance computing applications. These circuits can operate at very high frequencies (tens of GHz) but consume very low power (from nanowatts to microwatts per gate). Energy-efficient SFQ (ERSFQ) circuits, evolved from traditional rapid SFQ (RSFQ) circuits, were invented with the goal of elimination of static power dissipation. When compared with RSFQ circuits, ERSFQ circuits require a new biasing network that includes biasing Josephson junction(s), biasing inductor(s), and feeding Josephson transmission line(s). Some general suggestions on how to design the network have been offered, but a detailed analysis and optimization scenario for the network is still to be provided. In this paper, we first optimize the previously reported DC-biased two-Josephson junction per bit RSFQ shift register circuit, which can be used to provide a more robust, energy-efficient, and high memory capacity storage unit. The simulated power dissipation of 16-bit RSFQ shift register is 0.45 mu W per bit when operating at 21.7 GHz. We then convert the RSFQ-based shift register into an ERSFQ structure and investigate the effects of the ERSFQ bias network on the margins of the ERSFQ circuit. Finally, we propose a more comprehensive optimization method for the ERSFQ biasing network.

As superconducting circuits grow in complexity, full transient simulation and verification at the Josephson junction level using analog circuit simulators become increasingly computationally expensive. To enable faster functional and timing verification using timing back annotation and static timing analysis, logic models of rapid single flux quantum library cells are developed using hardware description languages like Verilog together with the required timing characteristics. These include propagation delays and minimum pin-to-pin pulse arrival time separation at various process and operating corners. These timing parameters must satisfy required margins and yield using Monte Carlo simulations with statistical variations. For each library cell, these timing parameters depend not only on the adjacent cells but also on their internal states. These delay variations are driven by bias current redistribution, load inductance, and load junction critical currents. We present our methodology for extracting these timing parameters to enable timing back annotation and static timing analysis. We demonstrate our methodology with a parallel counter as a reference circuit and show that timing back annotated simulation can closely match results from full circuit simulation.

The increasing complexity of modern rapid single flux quantum (RSFQ) circuits has made on-chip signal routing, an issue of growing importance. In this paper, several methods for routing large-scale RSFQ circuits are described, and a process is presented for determining when to use passive microstrip transmission lines (PTL) and active Josephson transmission lines (JTL). The effect of the size of the JTL inductor and Josephson junctions on the length of a JTL chain for a target delay is also discussed. The dependence of the JTL inductance on the physical layout is evaluated, and the effects of the primary PTL parameters on delay are characterized. A novel PTL driver and receiver configuration is also proposed. Tradeoffs among the number of JJs, inductance, and length of a PTL stripline in the receiver and driver circuits are reported. The energy dissipation is evaluated for two different interconnects. A tradeoff between the proposed PTL circuits and an optimized JTL in terms of energy dissipation and delay is discussed. Guidelines for choosing the optimal element values are determined, and a simulated bias margin of $\pm$ 29% for the bias current of the proposed receiver operating at 20 GHz in a 10 kA/cm $^2$ technology for a 1-mm transmission line is achieved. Summarizing, guidelines and design tradeoffs appropriate for automated layout and synthesis are provided for driving long interconnect in SFQ VLSI circuits.

Nb/Al-AlO x /Nb Josephson junctions are widely used in superconducting quantum interference devices and rapid single flux quantum (RSFQ) circuits. Very large-scale RSFQ integration often has a strict requirement on wafer-scale junction qualities. In particular, Nb film stress in Nb/Al-AlO x /Nb trilayer based Josephson junctions is a critical factor affecting their qualities. In this work, we develop a multi-step sputtering process to prepare Nb films with different combinations of stress and roughness to investigate the correlation between Nb film stress and junction quality. In particular, this method allows us to prepare Nb films with almost the same roughness but different stress, a key factor to study solely the influence of stress on junction qualities. Our measurements indicate that within a very tight range of film roughness (less than 2 nm), tensile film stress is found to decrease the quality of Nb/Al-AlO x /Nb Josephson junctions and larger film roughness has a positive effect on junction quality. By decreasing the total tensile stress and increasing the film roughness properly, we fabricated Nb/Al-AlO x /Nb Josephson junctions with a high quality factor characterized by $R_{sg}/ R_{N}$ (30 on average). The minimum size of junctions was 1 μm.

Long ago, current recycling or serial biasing technique was recognized as a promising solution for the reduction of bias current in VLSI dc biased digital superconductor circuits. Despite a significant number of declarations, not so many successful experiments have been reported so far. In the paper we discuss our recent experiments with serially biased 16-bit counter-flow RSFQ shift registers, connected by special interfaces that are able to transfer SFQ pulses between the galvanically isolated driver and receiver. The required functionality is achieved using a superconductor transformer with isolated input and output coils. The known drawback of such interfaces is their parasitic sensitivity to magnetic fields induced by remote currents. To depress this sensitivity we have implemented a special superconductor guard that uses six superconductor layers. We have achieved stable operations of such registers with 16 current recycling stacks. The circuits have been fabricated at MIT Lincoln Laboratory.

Energy-efficient rapid single flux quantum (ERSFQ) circuits have become a viable alternative for the implementation of superconducting circuits due to a large amount of static power consumption in RSFQ circuits. ERSFQ circuits are built upon the popular RSFQ logic circuits by replacing the power-dissipating resistor bias network with a bias network consisting of active devices. In this paper, a simulation study of ERSFQ biasing scheme is carried out by building simulation test benches for both synchronous and asynchronous ERSFQ circuits. A study is carried out to present the optimum value of biasing inductance, influence of the feeding Josephson transmission line (FJTL) and the effect of its size, the effect of the feeding clock frequency, and the effect of the circuit operating frequency. An innovative clock-choking mechanism using magnetic Josephson junctions is also proposed for the FJTL in the case of no logic circuit activity for a current-recycling circuit block, which would help in eliminating the dynamic power consumed due to the switching of bias junctions in a logic circuit. Simulation results for current recycling ERSFQ circuits are presented along with a strategy for implementing large superconducting circuits.

In this chapter, the most popular type of superconductive digital logic—rapid single flux quantum (RSFQ) logic—is described. The basic building blocks of digital RSFQ circuits are described in this chapter. Different types of transmission lines for this technology—JTL and PTL—are introduced, and the advantages and disadvantages of these interconnect structures are discussed. Certain basic structures of RSFQ circuits, flux storage loops, balanced comparators, and buffers, are described here as a framework to demonstrate the operation of more complex gates. Bias current distribution in RSFQ circuits is also discussed in this chapter. Resistive bias distribution, commonly used in RSFQ circuits, is described, and the disadvantages of this approach are reviewed. Energy efficient modifications to RSFQ logic to reduce or eliminate static power dissipation are also introduced, along with the advantages and disadvantages of these different circuit topologies. In particular, the ERSFQ bias scheme, which utilizes inductive current distribution with JJs as current regulators and feeding JTLs as voltage references, is introduced.

The primary operation of any processor is to perform basic arithmetic operations. In all basic arithmetic operations, multiplication consumes more time to be performed. Multiplier is the component which performs the multiplication operation. Its performance speed is going to affect the speed of the entire processing unit. The major operation of multiplier is to generate final product from partial products. To perform this major operation, the required architecture may require more area which intends to increase in latency in operation. In order to improve the performance of processor with minimum area, fast multiplier must be employed to perform multiplication operation. With high speed, the multiplier should occupy less area and consume low power. In the design of multipliers, a new technology called superconductor RSFQ logic is extensively used in order to achieve a multiplier design with less area and minimum latency in operation. From the time of introduction of this technology, different types of RSFQ multipliers are proposed. This paper gives an comparative analysis of rapid single flux quantum(RSFQ) technology multipliers like integer multiplier, matrix multiplier, parallel carry-save pipelined multiplier, floating-point multiplier in terms of area (number of Josephson junctions) and latency.

Rapid single flux quantum (RSFQ) circuits have recently attracted considerable attention as a promising beyond CMOS technology for exascale computing. Unlike conventional CMOS circuits, RSFQ circuits require a specific bias current delivered to each Josephson junction, making robust bias networks an issue of great importance for large scale integration. ERSFQ is an energy efficient, inductive bias scheme for RSFQ circuits, where power dissipation is drastically lowered by eliminating the bias resistors while the cell library remains unchanged. An ERSFQ bias scheme requires the introduction of multiple circuit elements — current limiting Josephson junctions, bias inductors, and Josephson transmission lines. Multiple guidelines exist for the effective design of these structures. In this paper, additional parameter guidelines and design techniques are presented to decrease physical area and dynamic power dissipation while improving bias margins. These guidelines and techniques are applicable to automating the synthesis of bias networks to enable large scale ERSFQ circuits.

A Josephson junction is a device made of two superconducting electrodes separated by a very thin layer of isolator or normal metal. This relatively simple device has found a variety of technical applications in the form of Superconducting Quantum Interference Devices (SQUIDs) and Single Electron Transistors (SETs). One can expect that in the near future the Josephson junction will find applications in digital electronics technology RSFQ (Rapid Single Flux Quantum) and in the more distant future in construction of quantum computers. Here we concentrate on the relation of the curvature of the Josephson junction with its inductance. We apply a simple Capacitively Shunted Junction (CSJ) model in order to find condition which guarantees consistency of this model with prediction based on the Maxwell and London equations with Landau-Ginzburg current of Cooper pairs. This condition can find direct experimental verification. Keywords: Josephson junction, CSJ model, Fluxon

A design of a 32 × 32-bit 4-bit bit-slice integer multiplier for rapid single-flux quantum microprocessors is shown. The multiplier carries out both signed and unsigned multiplication. It is designed with synchronous concurrent-flow clocking and target frequency of 50 GHz using the AIST 1.0-μm Nb/AlO x /Nb, nine-layer advanced process 2 fabrication technology with a critical current density of 10 kA/cm 2. It consists of 56 885 Josephson junctions. The area is 12.00 × 6.65 mm2. The simulation results show correct operation with frequency of 50 GHz at the dc bias voltage of 2.5 mV. The throughput is 3.125 × 109 multiplications per second.

Bias lines routed over a ground plane naturally form microstrip lines associated with the presence of a capacitance. This can lead to unwanted resonances when coupled to Josephson junctions. This work presents an electrical model of a shunted Josephson junction with its bias lines and pads, fabricated with the 1 kA/cm$^2$ RSFQ niobium process of the FLUXONICS Foundry. A compact LCL T-model is used to simulate the microwave behavior of the bias line, predict resonances and design resonance-free superconducting circuits. The I-V characteristics of three shunted Josephson junctions have been obtained from time-domain simulations done with JSIM and show a good match with the global behavior and experimentally observed resonance at 230 GHz, measured at 4.2 K. The influence of the position and value of a series resistor placed on bias lines is studied to damp unwanted resonances at the junction., Presented at ISEC2019 conference

The Josephson balanced comparator is the key component of Single Flux Quantum logic devices because it is the decision making element. It is formed by two Josephson junctions (JJs) connected in series from a clocking perspective and in parallel for the current to be measured. Its noise properties are crucial for the performance of logic devices. The balanced comparator can also be used to monitor the fab process and design implementation as an indicator of excess noise, overheating, linearity, dynamic effects, etc. We designed several test structures to measure the comparator gray zone at different fabrication process nodes at MIT-LL. We used digital circuitry to measure comparator characteristics at low frequencies. An analog testbed was used to perform high-frequency characterization. Experimental results for different current densities, sheet resistances, damping and clock frequencies are presented.

Logic design of a 16-bit bit-slice shifter for 64-bit superconducting rapid single-flux-quantum (RSFQ) microprocessors is proposed. The shifter supports three types of shift operations including logic shift, arithmetic shift and rotating shift. Each of 64-bit shift input operands is divided into four slices of 16-bit each. In order to simulate the digital function and timing of the proposed 16-bit bit-slice shifter, we design a logic-level simulation model based on the Open Dataset of CONNECT Cell Library for AIST ADP2. As the results of simulation, the information of RSFQ circuits, such as the number of Josephson junctions, area and latency of the 16-bit bit slice shifter can be obtained. The simulation results show that the proposed 16-bit bit-slice shifter can work correctly.

As the scale of RSFQ circuits increasing, signal integrity issues of interconnects become critical. It is necessary to analyze time-domain response of coupled passive transmission lines in RSFQ circuits. In this paper, a method based on finite-difference time-domain (FDTD) method and the Newton-Raphson iterative algorithm is proposed to co-analyze 2-coupled passive transmission lines and Josephson junctions. The FDTD method is used to solve the telegraph equations of coupled passive transmission lines. And the Newton-Raphson iterative algorithm is adopted to solve the nonlinear equations of the boundary conditions. The simulation and numerical results show that the proposed co-analysis method has the same accuracy as WRspice and higher efficiency than WRspice.

Field Programmable gate arrays (FPGAs) are one of the most successful circuits in the semiconductor industry. In the absence of a reliable three-terminal switch like MOSFET for rapid single flux quantum(RSFQ) technology, it was difficult to implement FPGA like reconfiguralbe circuits. However, a recently proposed superconducting magnetic FPGA (SMFPGA) implements a controllable switch by controlling the critical current of magnetic Josephson Junctions (MJJs) placed in energy-efficient RSFQ bias network. For implementing a configurable logic block (CLB) with a smaller area for the said FPGA, we designed a reconfigurable gate that can implement four basic logical functions: AND, OR, XOR and NOT. The programmability to implement the four functions is achieved by introducing MJJs in the circuit at specific locations and programming their critical current. The gate is made reconfigurable by having the ability to change both the bias current at different ports and the critical current of a JJ in the gate to two different values. This makes the size of CLB ten times smaller compared to the earlier design and simplifies the SMFPGA. We describe the design methodology and the simulation results of the reconfigurable gate.

In this work under the IARPA SuperTools program we developed a layout synthesis tool with scripting support. The user specifies the relative positions of Josephson junctions and inductances constrained by a user-defined cell height and cell width. Tight integration with the three-dimensional inductance extraction tool, InductEx, allows inductances to be automatically generated while meeting reasonable design values. Based on these user inputs, the tool can synthesize the physical layout of logic cells for multiple SFQ circuit technologies according to design rules and layer parameters. Furthermore, it enables the straightforward regeneration of entire cell libraries when design rules change or when libraries have to be redesigned for more advanced fabrication processes. We describe the methodology of our synthesis tool and show the results applied to both RSFQ and AQFP logic families.

Rapid Single Quantum Flux (RSFQ) logic, based on Josephson Junctions (JJs), is seeing a resurgence as a way for providing high performance in the era beyond the end of physical scaling of CMOS. Since it uses fabrication processes with large feature sizes, the defect density for RSFQ is dramatically lower than its CMOS counterpart. Hence, process variations and other RSFQ-specific non-idealities become the major causes of chip failures. Because of the nature of its quantized pulse-based operation, even highly-distorted pulses are interpreted logically correctly by cells, but the timings is affected. Therefore, timing verification and delay testing increase in importance in RSFQ. In this paper, we address several radically new phenomena in RSFQ technology, especially the existence of single-pattern delay tests and the need to propagate delayed values via multiple pipeline stages. We then characterize cells under process variations and identify delay excitation conditions, sensitization conditions, and conditions for propagation of the logic errors caused by process variations. We then propose a completely new ATPG paradigm which utilizes these new phenomena to select target delay subpaths and generate test patterns that are guaranteed to excite the worst-case delay along each target delay sub-path. Finally, we present Monte Carlo simulation results for benchmark circuits with process variations to demonstrate the effectiveness of the vectors generated by our new ATPG.

Design and manufacturing of superconductive electronics have been evolving over the past three decades with significant progress made in related fields. Rapid single flux quantum (RSFQ) logic circuits have become popular among superconductive logic families and its energy-efficient variants (ERSFQ and eSFQ) have shown promise as an ultra lowpower and high-speed circuit fabric. SFQ circuits have been demonstrated at tens of GHz with an energy consumption of an attojoule per gate. There are many differences between SFQ and conventional CMOS circuits. SFQ logic circuits are based on the manipulation of the quantized magnetic flux pulses. Most of the logic gates are sequential in nature requiring the clock to be distributed to every logic gate. SFQ logic gates have no gain and hence splitters are needed to drive multiple fanouts. Design and successful demonstration of a controllable superconducting switch and a compact reliable memory element have evaded researchers so far. This paper starts by describing key differences between SFQ logic and conventional CMOS and concludes by listing key challenges that must be overcome to achieve the very large scale integration of SFQ circuits and make the demonstration of a superconductive CPU a reality.

Majorana bound states (MBSs) can occur in Josephson junctions of conventional s-wave superconductors coupled via a strong topological insulator. In configurations of multiple line junctions meeting at a point, the criterion for the MBS to exist coincides with the presence of a fractional Josephson vortex with 2π phase winding. We investigate the dynamic stability of such vortices in arrays of tri- and quad-junctions. The existence of fractional vortices in arrays is demonstrated, but the dynamic stability is found to depend critically on the current-phase relation and the inductance. We propose the idea, and study the feasibility, of manipulating the location of the vortices in arrays by using current pulses, compatible with rapid single flux quantum technology. It is shown theoretically, using a modified resistively shunted junction model, that braiding operations can be achieved using current pulses injected from the edge of the array. It is necessary to use vortex sites with elevated critical current as traps.

Switching time limitations of the ac bias current of Josephson junctions in bidirectional rapid single flux quantum (RSFQ) logic circuits are investigated in order to determine the limits to the maximum possible operating frequency. We introduce a new approach based on modifying the bias current parameters and determining the inductance values in the circuit for reducing the switching transition time of the bias current through the junctions. We have simulated and optimized the timing and the operation of the bidirectional nondestructive readout and Josephson transmission line cells in this respect to demonstrate the results of utilizing the proposed approach. We successfully reduced the unwanted spike-type signals across the inductances which are made through the transitions during the fast switching times limiting the operation frequency. This is while we have also removed the consequent destructive spikes at the output. We have included the effects of other determining parameters of the circuit in this investigation and found their relatively optimal values to improve the temporal behavior of the bidirectional RSFQ cells. The results of the proposed approach leading to the fastest possible operation of the considered gates obtained in this work are thoroughly reported.

We propose a new inductive- and resistive- (LR) biased low-power single-flux quantum (SFQ) circuit that has a dynamic resetting mechanism of the bias current. Because the bias current returns to the initial state rapidly by switching of a Josephson junction in the bias circuit after circuit operation, the operating frequency of the LR-biased SFQ circuit can be improved. We simulated a Josephson transmission line (JTL) that employs the proposed biasing scheme and evaluated the bias current recovery time. Circuit simulation results show that the bias current recovery time of the proposed circuit is improved by 10-20% compared to that of the conventional LR-biased JTL. We have designed and measured a 10-stage JTL and an 8-bit concurrent-flow shift register (SR) with the proposed biasing scheme. We have experimentally demonstrated operation of the JTL with the bias margin of ±29.4% at the operating frequency of up to 70.4 GHz and operation of the 8-bit SR up to 12.3 GHz by the on-chip high-speed test.

We present a design of an 8-bit bit-serial rapid single-flux-quantum (RSFQ) microprocessor, which is called CORE e4, and its high-speed functionality test results. The CORE e4 is equipped with four general-purpose registers and can execute 20 different instructions. The first version of the CORE e4, which is called CORE e4v1, has been implemented using the National Institute of Advanced Industrial Science and Technology (AIST) 10-kA/cm 2 advanced process (ADP2) and the CONNECT cell library. The CORE e4v1 consists of approximately 7000 Josephson junctions and occupies a circuit area of 3.00 mm × 1.98 mm. The estimated power consumption and performance are 2.03 mW and 333 million instructions per second, respectively. CORE e4 is one of the highest performing RSFQ microprocessors.

In addition to their fast switching with low power dissipation, precise voltage generation is a unique feature of single-flux-quantum (SFQ) circuits. This feature is attractive for realizing ac voltage standards consisting of SFQ-based digital-to-analog converters (DACs). Among several key components in SFQ-based DACs, a double-flux-quantum amplifier (DFQA) is a potential candidate to amplify the output voltage. In this paper, we present a redesigned DFQA without flux bias lines. We found a parameter set that provided wide bias margins and zero-flux-bias operation. Improved bias regions were numerically demonstrated, whereas a ±20-fold DFQA excluding flux biases was fabricated using Nb integration technology and tested in a liquid helium bath.

Half-flux-quantum (HFQ) circuits store and propagate half-flux quanta. The basic circuit element is a 0-π SQUID, which is a superconducting quantum interference device with a conventional Josephson junction (0-junction) and a π-shifted ferromagnetic junction (π-junction). A 0-π SQUID achieves a small critical current in the absence of an external magnetic field, thus reducing power consumption. It is easy to set up 0-0-π SQUIDs with two 0-junctions and a π-junction which serves as a π phase-shifter. We simulated 0-0-π SQUID-based HFQ circuits driven by low bias voltages, referred to as LV-HFQ circuits. In these circuits, shunt resistors are not required for switching junctions because there is no hysteresis in the current–voltage characteristics of 0-0-π SQUIDs. We estimated the power consumption and maximum operating frequency of an HFQ Josephson transmission line based on 0-0-π SQUIDs. When operating at 43.5 GHz, the power dissipation of a single element composed of a 0-0-π SQUID and a bias resistor fell to about 0.165 nW when biased at 60 μV. The LV-HFQ circuit is potentially more power-efficient than all other currently available superconducting logic circuits.

Single Flux Quantum (SFQ) electronic circuits originated with the advent of Rapid Single Flux Quantum (RSFQ) logic in 1985 and have since evolved to include more energy-efficient technologies such as ERSFQ and eSFQ. SFQ logic circuits, based on the manipulation of quantized flux pulses, have been demonstrated to run at clock speeds in excess of 120 GHz, and with bit-switch energy below 1 aJ. Small SFQ microprocessors have been developed, but characteristics inherent to SFQ circuits and the lack of circuit design tools have hampered the development of large SFQ systems. SFQ circuit characteristics include fan-out of one and the subsequent demand for pulse splitters, gate-level clocking, susceptibility to magnetic fields and sensitivity to intra-gate and inter-gate inductance. Superconducting interconnects propagate data pulses at the speed of light, but suffer from reflections at vias that attenuate transmitted pulses. The recently started IARPA SuperTools program aims to deliver SFQ Computer-Aided Design (CAD) tools that can enable the successful design of 64 bit RISC processors given the characteristics of SFQ circuits. A discussion on the technology of SFQ circuits and the most modern SFQ fabrication processes is presented, with a focus on the unique electronic design automation CAD requirements for the design, layout and verification of SFQ circuits.

Josephson junction-based superconducting logic families have been proposed to implement analog and digital signals, which can achieve low energy dissipation and ultra-fast switching speed. There are two representative technologies: DC-biased RSFQ (rapid single flux quantum) technology and its variants that achieve a verified speed of 370 Ghz, and AC-biased AQFP (adiabatic quantum-flux-parametron) that achieves an energy dissipation near quantum limits. Despite extraordinary characteristics of the superconducting logic families, many technical challenges remain, including the choice of circuit fabrics and architectures that utilize the SFQ technology and the development of effective design automation methodologies and tools. This paper presents our work on developing design flows and tools for DC- and AC-biased SFQ circuits, leveraging unique characteristics and design requirements of the SFQ logic families. More precisely, physical design algorithms, including placement, clock tree routing, and signal routing algorithms targeting RSFQ circuits are presented first. Next, a majority/minority gate-based automatic synthesis framework targeting AQFP logic circuits is described. Finally, experimental results to demonstrate the efficacy of the proposed framework and tools are presented.

Sandwich-type MgB 2 /MgO/MgB 2 Josephson junctions with sizes ranging from 0.5 μm × 0.5 μm to 10 μm × 10 μm were fabricated using electron beam lithography. The junctions show critical current densities as high as 130 kA/cm 2 . The smallest of the junctions operated free of hysteresis below 4.2 K. They may be ideal for use in rapid single flux quantum circuits with no requirement for external shunt resistors. The 10-μm junctions show good agreement with the expected Fraunhofer-like modulation of critical current with magnetic field; however, the smaller junctions show a sinusoidal modulation, indicating an anomalous current distribution that needs to be further investigated. Series arrays of Josephson junctions were made to quantitatively study the uniformity of junction parameters, which shows a 54% spread in critical current of a 100 junction array of 4-μm junctions.

We designed and fabricated rapid single-flux-quantum (RSFQ) circuits using a new 20-kA/cm 2 process based on conventional Nb/AlO x /Nb Josephson junction (JJ) technology. Circular JJs were fabricated to improve their uniformity. They had sufficiently low spread of the critical currents for large-scale RSFQ circuits. We selected the circuit design parameters carefully, including the bias voltage and McCumber-Stewart parameter, balancing the energy consumption, switching speeds, margins, and integration density. We demonstrated several logic gates and shift registers at a clock frequency of 154 GHz with the designed bias voltage of 2.5 mV, and demonstrated energy-efficient shift registers using the low-voltage RSFQ (LV-RSFQ) technique at 83 GHz.

We report on technique and results for superconductor electronics fabrication process, featuring customizable number of planarized superconducting layers. The novel technique enhanced yield on stackable vias of our standard planarized process (RIPPLE) by eliminating the need for an additional deposition of aluminum as an etch stop in the metal-via stack. The drawback of the previous approach was the difficulty in processing aluminum using either wet or dry etch mechanisms. Here, we discuss details of the novel fabrication process flow and its realization for 4.5 kA/cm2 fabrication process with six Nb layers with two fully planarized layers. We report test results of various planarization diagnostics structures, accounting the influence of topology on Josephson junction quality, as well as yield and critical current of via stacks. We also report on inductance measurement results providing information on interlayer dielectric thickness for planarized layers; confirming a good uniformity over the wafer. Basic components of superconducting logic such as dc/SFQ, SFQ/dc converters, Josephson transmission lines (JTLs), and simple digital circuits such as half-adder (HA) have been designed, fabricated and tested using either conventional (RSFQ) or energy-efficient (ERSFQ) approach. The ERSFQ HA cells with bias inductors fabricated in two planarized layers were shown to function with the operational margins of +/-22%.

We have fabricated and tested rapid single flux quantum toggle flip-flop circuits using self-shunted MgB 2 / MgO/MgB 2 Josephson junctions with a single ground layer. The MgB 2 films were deposited using HPCVD, and the MgO barrier was deposited using DC reactive sputtering. We highlight the circuit's voltage divider operation dependence on current bias and temperature which show operation from 7 to 30 K. The highest attained operating speed is 335 GHz at 7 K. These results demonstrate the versatile temperature range and speed of MgB 2 digital circuits.

A test point insertion technique for enhanced testability in superconductive RSFQ logic is proposed here. Test point insertion reduces the overhead of a set/scan chain while maintaining most of the functionality. The SFQ multiplexers are replaced with mergers and blocking gates. The multiplexer control signals are replaced with a gated clock signal. Clocked blocking gates are used to disable undesired data input. The proposed technique requires 35% fewer Josephson junctions as compared to multiplexers when applied to a 64-bit register. This technique can be utilized to evaluate error prone SFQ circuits and for built-in self-test of SFQ compatible memory systems.

For spectroscopic and imaging applications in the submillimeter wavelength band, superconducting radiation sensors are widely used. Thereby, sensor arrays with a rising number of pixels require multiplexing techniques in order to reduce the number of wires leading to the cryogenic stage. A current steering switch (CSS) provides the basis for one kind of promising code division multiplexers. It is composed of two identical superconducting quantum interference devices (SQUIDs) in parallel current paths. Switching one of them from the superconducting into the normal state, which is controlled by the applied magnetic flux, alters the signal path; thus, they can act as a polarity switch for analog signals. In this paper, we describe a method that uses rapid single-flux quantum (RSFQ) electronics for controlling these switches. Therefore, their SQUIDs are inductively coupled each to the storing loop of an RSFQ delay flip-flop (DFF); hence, the state of the analog switch can be controlled by means of digital RSFQ signals. As a first step, we show the change in the critical current of the SQUIDs by the coupled operating digital circuit. For a wider operating range of the CSS, we developed a DFF, which is able to store a larger quantity of magnetic flux to make it possible to apply more flux to the coupled SQUID. For further improvements, we tested asymmetric SQUIDs to reduce the required magnetic flux. The results of the simulations and measurements are discussed.

Superconducting Quantum Arrays (SQAs) based on integration of quantum cells each consisting of two Josephson-junction parallel arrays [Differential Quantum Cell (DQC)] are analyzed for applications in broadband radio frequency systems. These SQAs are capable of providing highly linear magnetic signal to voltage transfer with high dynamic range. Both detail study of the quantum cells with realistic parameters and analysis of their characteristics, including voltage response linearity, are presented and discussed. A prototype of an active electrically small antenna is implemented based on an SQA containing 560 DQCs. We demonstrated the SQA voltage response swing as high as $\sim$ 100 mV at a transfer factor of $\sim\!\! 6.5\ \hbox{mV}/\mu\hbox{T}$ .

We propose a controllable and scalable architecture for quantum information processing using a superconducting system network, which is composed of current-biased Josephson junctions (CBJJs) as tunable couplers between the two superconducting transmission line resonators (TLRs), each coupling to multiple superconducting qubits (SQs). We explicitly demonstrate that the entangled state, the phase gate, and the information transfer between any two selected SQs can be implemented, respectively. Lastly, numerical simulation shows that our scheme is robust against the decoherence of the system.

This review is devoted to a discussion of the prospects for solving the problem of a low degree of integration of the traditional elements for promising (due to the high performance and extremely low energy dissipation) superconducting digital electronics. We define three main directions on the path to compact multi-element Josephson electronic systems: (1) reduction of the Josephson junction to submicron size, (2) decrease of the area of standard logic cells, and (3) fabrication of a compact and rapid Josephson memory. We present the physical foundations of Josephson elements in order to show the fundamental constraints on establishing standard submicron tunnel contacts and compact logic cells/memory elements. This survey clearly demonstrates the essence of breakthrough technological solutions to create ultrasmall heterostructures with desired settings, reduce and optimize logic cells, and create memory unit cells based on Josephson junctions with magnetic layers.

In this chapter we present results of achievement of modern analog superconducting electronics. In first section we discuss physical foundation and characteristics of superconducting edge bolometers. The influence of HTS materials on the characteristics is analyzed. Second section deals with description of samplers based on JJs. Two types of comparators-on single junction and balanced comparators are discussed. Presented results of linear theory for the estimation of time resolution of JJ comparators. Comparators using RSFQ technique discussed and ultimate characteristics presented. Third section is devoted to AC and DC SQUID magnetometers . Firstly, single and two-junction interferometers, the influence of d-wave order parameter symmetry on the characteristics are described. Furthermore, using these interferometers as sensitive elements of SQUIDs and characteristics is presented. Next section devoted to description of current state of superconducting microwave devices. Last topics in this chapter are using JJs in meteorology and description of multi-terminal superconducting devices.

Two superconductors coupled by a weak link support an equilibrium Josephson electrical current which depends on the phase difference $\varphi$ between the superconducting condensates [1]. Yet, when a temperature gradient is imposed across the junction, the Josephson effect manifests itself through a coherent component of the heat current that flows oppositely to the thermal gradient for $ \varphi, Comment: 10 pages, 9 color figures

Conventional Josephson junctions are used to build superconducting quantum interference devices (SQUIDs) which are the most sensitive magnetic field sensors known. Today, SQUIDS are widely used in many different areas like medical and biological research and diagnostics, geophysics, non-destructive evaluation of materials and structures, or fundamental physics research. In recent years the highly anisotropic and unique intrinsic properties of YBa2Cu3O7- x superconducting nano-films allowed fabrication of a special type of Josephson junctions, so-called π-junctions, which are excellent candidates as building block for fast, low-dissipative superconducting digital electronics or quantum computation. For those reasons fabricating high quality and reliably Josephson junctions has been one of the priority areas of research in superconductivity. There are several well-established technologies to fabricate Josephson junctions made of YBa2Cu3O7-x superconducting nano-films. Here I will briefly describe two of the most important ones used to fabricate both conventional Josephson junctions and π-junctions.

Direct Current Superconducting QUantum Interference Devices (dc SQUIDs) are sensors for the detection of magnetic flux or any physical quantity that can be transformed into magnetic flux. They consist of a superconducting loop interrupted by two resistively shunted Josephson tunnel junctions. Typically operated at 4.2 K, they exhibit magnetic flux noise levels of the order of 1 μΦ0/Hz1/2, corresponding to a noise energy of 10−32 J/Hz1/2. They can be used for example as magnetometers, magnetic gradiometers, current sensors and voltmeters, susceptometers or (rf) amplifier. With their large bandwidth and flat frequency response ranging from dc to GHz, they are excellent suited for a wide variety of applications, such as e.g. biomagnetism and geophysical exploration to the detection of gravity waves and magnetic resonance.

We present a microwave quantum refrigeration principle based on the Josephson effect. When a superconducting quantum interference device (SQUID) is pierced by a time-dependent magnetic flux, it induces changes in the macroscopic quantum phase and an effective finite bias voltage appears across the SQUID. This voltage can be used to actively cool, well below the lattice temperature, one of the superconducting electrodes forming the interferometer. The achievable cooling performance combined with the simplicity and scalability intrinsic to the structure pave the way to a number of applications in quantum technology.