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In this letter, a novel edge termination named deep junction termination for silicon superjunction (SJ) MOSFETs is proposed, simulated, and experimentally demonstrated for the first time. By utilizing a typical implantation-and-epitaxy process to form P- and N-pillars for SJ, it is possible to form deep junctions as the device termination with a large radius of curvature and lateral and vertical doping gradation. The 2-D simulation shows that more than 700-V blocking voltage (BV) can be achieved by a 57- \mu \textm drift layer with this novel termination, and experimentally BV as high as 660 V is demonstrated by the fabricated device. [ABSTRACT FROM AUTHOR]

A novel diagonal square array junction barrier Schottky (JBS) diode is created to enhance the forward current and reverse breakdown voltage by increasing the Schottky contact area and shortening the diagonal spacing between two adjacent p+ islands in the active area of a JBS diode. The shape of the p+ islands is square and the positional arrangement of the p+ islands is a diagonal array. Half of the upper and lower p+ islands with smaller areas are connected with the innermost p+ guard ring to create more Schottky contact area and laterally extend the electric field to the edge termination. Results show that the forward current density and reverse breakdown voltage for the diagonal square array JBS diode are 4.2% and 10.7% higher than those for the conventional square array JBS diode, respectively. As the spacing increases, the breakdown voltage for the diagonal square array JBS diode and the conventional square array JBS diode decrease by 3.5% and 7.3%, respectively, indicating that the diagonal square array JBS has more uniform depletion regions and electric field to retain the breakdown voltage. [ABSTRACT FROM AUTHOR]

In this paper, a comparison of different techniques for SiC high-voltage devices is performed using numerical simulations. In particular, the method of counter doping (CD) introduced in the junction termination extension (JTE) region to create a multizone termination effect is investigated. Simulation shows that compared with the other edge termination techniques, CD-JTE greatly reduces the sensitivity of breakdown voltage (BV) to JTE doses and surface charges. The multizone CD-JTE with outer rings shows that for a 30- \mu m thick epi-layer, 90% of the theoretical BV is achievable with a wide tolerance of 11\,\times \,10^{\mathrm {12}} /cm ^{2} to the JTE dose and 85% of the theoretical BV with an increased tolerance of 6.19\times 10^\mathrm 12 /cm ^2 to the positive surface charges, both superior to other JTE structures investigated in this paper. [ABSTRACT FROM AUTHOR]

Design and fabrication of 4H–SiC lateral high-voltage devices on semi-insulating substrates based on the charge compensation principle have been investigated in this work. In the simulation, field plates are critical in relieving the electric field crowding at junction corners at high reverse biases. By incorporating field plates with proper lengths, the breakdown voltage (BV) of a single-zone reduced-surface-field (RESURF) device with a 100- \mu\m drift region can be improved from 3360 to 5880 V. The BV can be further enhanced to 8000 V by using a two-zone RESURF structure. The reduction in BV by 10% charge imbalance variation is also improved from 49% for a single-zone structure to 36% for a two-zone structure. Simulation also shows that oxide charges and other surface charges will offset the optimized charge imbalance conditions and, therefore, should be considered in design if the amount is significant. A 4H–SiC JFET with a two-zone RESURF region was fabricated to demonstrate the advantages of lateral devices based on these concepts. The fabricated lateral 4H–SiC JFET has a BV of 4200 V and a specific on -resistance of 454 \m\Omega\cdot \cm^2. The figure of merit is as high as 38.8 \MW/cm^2. [ABSTRACT FROM AUTHOR]