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In this work, the deep-level transient spectroscopy (DLTS) is conducted to investigate the gate stack of the p-GaN gate HEMT with Schottky gate contact. A metal/p-GaN/AlGaN/GaN heterojunction capacitor is prepared for the study. The DLTS characterization captures the transient capacitance change in the stack, from which the capacitance of the metal/p-GaN Schottky junction can be extracted. By proper selection of the rate window, the impacts of the hole insufficiency effect are avoided during trap states evaluation. Thus, the information of deep energy levels in the p-GaN layer is revealed, which consists of an electron trap state with activation energy of 0.85 eV and a hole trap state with activation energy of 0.49 eV. The identification of these trap states in the p-GaN layer provides a physical foundation for understanding the threshold voltage instability in Schottky-type p-GaN gate power HEMTs. [ABSTRACT FROM AUTHOR]

Commercially available normally-off GaN power high-electron-mobility transistor (HEMT) devices have typically adopted a p-GaN gate structure. In the gate region, there exist a Schottky junction (between gate electrode and the p-GaN layer) and a p-GaN/AlGaN/GaN heterojunction. As the p-GaN layer is not directly shorted to the gate electrode and conducting channel, it can be considered as electrically “floating.” With drain voltage changing during a switching process, the variation of net charge in the floating p-GaN layer would cause instability in threshold voltage. Besides, because of the distinctive features of the p-GaN gate HEMT structure under certain gate/drain bias, gate-related junction capacitances would exhibit behavior different from those of a Si mosfet. Consequently, the switching transient performance of a GaN transistor with a p-GaN gate could be significantly influenced by the aforementioned factors. In this work, the threshold voltage instability associated with the drain-to-gate voltage stress is first analyzed. Despite the difficulty in directly performing capacitance measurements inside the device structure, a hybrid physical-behavior modeling method is proposed. The model is capable of extracting the capacitance bias relationships with regard to the gate region from static terminal measurements. In previous works, the advanced analytical model would make modest change on a Si mosfet's model. As a result, without fully considering the specific features of a GaN transistor with the p-GaN gate, the simulated waveforms would exhibit 20–50% discrepancy from the experiment. In contrast, the proposed switching transient analytical approach would exhibit improved accuracy (<10% disparity). Consequently, the switching transient performance of the GaN transistor with the p-GaN gate could be more accurately evaluated. [ABSTRACT FROM AUTHOR]

3-D edge termination design and analytic model for specific on-resistance ( R \mathrm{\scriptscriptstyle ON,\text {sp}}) versus breakdown voltage (BV) of a 700-V triple reduced surface field lateral double-diffused MOSFET (LDMOS) with n-type top layer are presented in this paper. To eliminate the premature avalanche breakdown induced by the electric field crowding and the local charge imbalance in the transition region of the source-centered edge termination structure, 3-D numerical simulations and experiments are performed to investigate two crucial parameters L1 and L2 in the layout of the transition region. It is observed that optimal electric field distribution is obtained and breakdown positions are transferred to the active region at L1 = 30~\mu \text{m} and L2 = 1~\mu \text{m} . On the other hand, an analytic model is developed to describe the relation between R \mathrm{\scriptscriptstyle ON,\text {sp}} and BV, which is obtained as R \mathrm{\scriptscriptstyle ON,\text {sp}} = 5.93 \times 10^{-6} \times 22({T}/298)^{1.7} \times \text {BV}^{2} and theoretically verifies that the fabricated device has achieved optimized R \mathrm{\scriptscriptstyle ON,\text {sp}} and BV. Compared with our previous paper, the LDMOS experimentally demonstrated improved performance with R \mathrm{\scriptscriptstyle ON,\text {sp}} of 86.49 \textm\Omega ~\cdot cm2 and BV of 805 V, which is leading performance for the 700-V applications in published data. [ABSTRACT FROM AUTHOR]

A 700 V dual-buried-layer n-channel lateral double-diffused MOSFET (DB-nLDMOS) based on substrate termination technology (STT) is presented and experimentally demonstrated in this paper. The termination region is well analyzed and designed to avoid the premature avalanche breakdown caused by the curved junction. The 2-D and 3-D numerical simulations have been performed to optimize the three key parameters of \Delta L1,\Delta L2, and \Delta L3 which impact on breakdown voltage (BV) greatly in the termination region. The simulation results show that the electric field peak is reduced and premature avalanche breakdown is avoided at the curved abrupt p-well/n-well junction with the STT. The experimental results demonstrate that low $R_{{\mathrm{\scriptscriptstyle ON},\mathrm {sp}}} of 105.6 \textm\Omega \cdot \mathrm cm^2 based on Ld and high BV of 788 V are achieved by the DB-nLDMOS. [ABSTRACT FROM PUBLISHER]

An analytical model for a novel triple reduced surface field (RESURF) lateral double-diffused metal–oxide–semiconductor (LDMOS) field-effect transistor with a low on-resistance n-type top (N-top) layer is proposed in this paper. The analytical model for surface potential and electric field distributions of the novel triple RESURF LDMOS is presented by solving the 2-D Poisson’s equation, which can also be applied in single, double, and conventional triple RESURF structures. The vertical and lateral breakdown voltages are formulized to quantify the breakdown characteristic. Besides, the optimal integrated charge of the N-top layer ( Q\textrm {ntop} ) is derived which can give a guidance for the dose of N-top layer. The triple RESURF LDMOS with a low on-resistance N-top layer is designed and manufactured according to the analytical model. All the analytical results can be well verified by numerical and measured results, showing the validity of the presented model. [ABSTRACT FROM AUTHOR]