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This brief proposes a low voltage ultra-low power 10-bit 100-MS/s successive approximation register (SAR) analog-to-digital converter (ADC). To overcome the performance degradation due to the signal-related current fluctuation under lower supply voltage, an adaptive-biasing comparator with current self-compensation (CSC) technique is proposed to obtain a constant working current, reducing the minimum supply voltage from 0.7V in conventional ADCs to 0.55V. Since full-scale range shrinks with the supply voltage, voltage undershoot in power rail caused by capacitor digital-to-analog converter (C-DAC) deteriorates effective-number-of-bits (ENOB). Conventional solutions involve enhanced regulators and large decoupling capacitors, which cost remarkable power dissipation and large chip area. This brief presents a pulse-injection undershoot compensation technique which reduces the DAC-related supply fluctuation from a typical 15mV to 1.8mV, and improves the ENOB by 0.4 bit. The prototype was fabricated in TSMC 28nm HPC CMOS technology. The proposed SAR ADC achieves an SNDR of 54.7dB and an SFDR of 68dB with the power consumption of 0.16mW under 0.55V supply voltage, a figure of merit (FoM) of 3.6-fJ/conversion-step is achieved. The chip area of the ADC core is 130μm×225μm.

Battery power has been a popular choice of delivering DC power to many portable RF systems including wireless sensor nodes/internet of Everything (IoE). An autonomously powered RF system of the orders of 100’s of µwatts is becoming increasingly popular in recent times because of integrated solutions in energy harvesting. The minimum sensitivity of an RF energy harvester and the targeted deliverable output voltage for a specific load resistance are dictated by threshold voltage of transistors used and reverse leakage of such transistors. A detailed look into the architectures of rectifiers can help tackle design problems in the RF-DC conversion process. So in this work we focused on the design of integrated RF energy harvesting by studying four important architectures of RF-DC converters. To achieve a fair comparison between these architectures, a matching network operating at 0.8 MHz is designed and applied for simulation. All of these converters are tested in LT-SPICE XVII using the same designed matching network and the rectifiers are implemented in 180 nm CMOS technology.

Now adays Very Large-Scale Integration (VLSI) circuits have good or great demand. Because CMOS circuit design having less power consumption. Transistors on the chip is doubled every two years, according to Moore’s law. So, it means transistor size is decreasing. This leads to increase the chip density and decrease the device size. The write and read depending on the bitline and bitline bar discharging and charging. When design the memory in below 16 nm uses Fin Field effect Transistor (FinFET) technology instead of CMOS (Complementary metal oxide semiconductor field effect transistor). Because to avoid short channel effect. Comparing leakage power, dynamic power and static power at 90 nm technology and write delay, read delay at both 90 nm and 45 nm technology in nine transistors (9 t), eight transistor (8 t) and six transistor (6 t) sram cell.

Demand for coarse grain reconfigurable architectures (CGRAs) has significantly increased in recent years as architectures need to be both energy efficient and flexible. However, most CGRAs are optimized for performance instead of energy efficiency. In this work a novel paradigm for reconfigurable architectures, Blocks, is presented. Blocks uses two separate circuit-switched networks, one for control and one for the data-path. This enables run-time construction of energy-efficient application-specific VLIW-SIMD processors on a reconfigurable fabric. Its energy efficiency is demonstrated by comparing Blocks to four reference architectures, a VLIW, an SIMD, a commercial low-power microprocessor, and a traditional CGRA. All comparisons are based on commercial low-power 40nm CMOS layout, including memories. Results show that Blocks can achieve a mean total energy reduction of 2.05x, 1.84x, 8.01x, 1.22x over a VLIW, an SIMD, an energy-efficient microprocessor and a traditional CGRA respectively. At the same time, Blocks delivers equal or higher performance per area due to its ability to adapt to applications by reconfiguration.

Since spiking neural networks can effectively simulate the information processing mechanism of the biological cortex, they are expected to bridge the gap between neuroscience and machine learning. The hardware simulation of large-scale spiking neural networks requires a simple and versatile silicon neuron model framework. In this paper, a spiking neuron circuit as the core device of spiking neural networks is presented. The proposed neuron circuit can mimic the dynamics of different types of biological neurons by adjusting the bias voltage. In order to facilitate the implementation of the spiking neuron circuit based on complementary metal-oxide-semiconductor (CMOS) and reduce the overhead of the circuit area, a modified Mihalas-Niebur mathematical model is adopted. The improved Mihalas-Niebur model is biologically plausible and can still successfully display all dynamic behaviors observed in biology. The function of the proposed neuron circuit has been verified by the phase diagram analysis method. The simulation results show the designed neuron circuit can successfully replicate 15 of the 20 firing patterns exhibited by the biological cortex, which proves that the neuron can act as a universal spiking neuron in very large-scale integrated circuit (VLSI) neuromorphic networks.

Offering a combination of low latency, high energy-efficiency, and flexibility, field-programmable gate arrays (FPGAs) suit applications ranging from Internet of Things (IoT) computing to artificial intelligence (AI). The conventional static random access memory (SRAM) FPGAs face severe challenges including large standby power and low logic density due to utilization of SRAM cell and MOS switch for signal routing. In response, researchers have introduced emerging non-volatile (NV) memory technologies to solve standby power issues. However, access transistors used for NV memory cell configuration still consume a large silicon area. In this article, we introduce an NV via-switch (VS) FPGA featuring fully back-end-of-line (BEOL) signal routing and front-end-of-line (FEOL) logic computing for high logic density. The VS fabricated in BEOL is constructed by two Cu atom switches (ASs) for signal routing and two a-Si/SiN/a-Si varistors for AS configuration. We demonstrate the first implementation of the VS-FPGA at 65-nm node and evaluate its performance by various basic applications. 2.6x logic density, 1.5x energy efficiency, and 1.4x operation speed are achieved in comparison with a previous complementary AS (CAS) FPGA in which one access transistor is necessary for each CAS configuration.

Small and low-cost chlorophyll sensors are popular in agricultural sector and food-quality control.Combining such sensors with silicon CMOS electronics is challenged by the absence of silicon-integrated light-sources.We experimentally achieve optical absorption sensing of chlorophyll based pigments with silicon (Si) micro light-emitting diodes (LED) as light-source, fabricated in a standard SOI-CMOS technology.By driving a Si LED in both forward and avalanche modes of operation,we steer its electroluminescentspectrum between visible (400-900 nm) and near-infrared (1120 nm). For detection of chlorophyll in solution phase, the dualspectrum light from the LED propagates vertically through glycerol micro-droplets containing sodium copper chlorophyllin at varying relative concentrations. The transmitted light is detected via an off-chip Si photodiode. The visible to near-infrared color ratio (COR) of the photocurrent yields the effective absorption coefficient. We introduce the LED-specificmolar absorption coefficient as ametric to compute the absolute pigment concentration (0.019 ± 0.006 mol L-1) and validate the results by measurements with a hybrid spectrophotometer. With the same sensor, we also show noninvasive monitoring of chlorophyll in plant leaves. COR sensitivities $\sim 3.9 \times 10^{4}$ mol-1L and $\sim 5.3 \times 10^{4}$ mol-1L are obtained for two leaf species, where light from the LED propagates diffusely through the thickness of the leaf prior to detection by the photodiode. Our work demonstrates the feasibility of realizing fully CMOS-integrated optical sensors for biochemical analyses in food sector and plant/human health.

Power Supply Noise (PSN) in CPU cores or any integrated circuit (IC) chips is a problem of power line voltage degradation impelled due to the parasitic components (viz., resistance, capacitance and inductance) across the packaging. This lowers the operating frequency of the silicon chip during high volume manufacturing and thereby affects the overall performance. After numerous attempts to minimize the parasitic impacts of power delivery networks (PDN) in IC packages, researchers also started to look for circuital configurations that can curb down the coefficients of PSN (i.e., the instantaneous current i(t) and the current ramp di(t)dt during OFF to ON switching of packaged CPU/IC). Though variable frequency clock (VFC) has emerged as a potential solution, its design is found to be complex and power hungry. Hence, a novel and simple configuration of VFC embedded with leakage control transistor based clock gating (LCT-CG) is tendered in this article, where the pertaining circuits and integrated system have been designed using UMC 65nm CMOS with a supply of 1.1V. The performance of the design is tested on Master-Slave Flip-Flop (MSFF) and a few prominent benchmark circuits (viz., ISCAS’89 s27, s820, s832, s1196, s9234 and ITC’99 b02 and an IEEE 754 complaint single precision FPU) considering the PDN of existing CPU OLGA package. The system level validation of our proposed IC on A-Z80 CPU chip offers the average power and PSN to be mitigated by 30.06% and 42.63% against the conventional clocking.

High-Voltage power Integrated Circuits (HVICs) are widely used to realize high-efficiency power conversions (e.g., AC/DC conversion), gate drivers for power devices and LED lighting, and so on. The Bipolar-CMOS-DMOS (BCD) process is proposed to fabricate devices with bipolar, CMOS, and DMOS modes, and thereby realize the single-chip integration of HVICs. The basic integrated technologies of HVICs include High-Voltage (HV) integrated device technology, HV interconnection technology, and isolation technology. The HV integrated device is the core of HVICs. The basic requirements of the HV integrated device are high breakdown voltage, low specific on-resistance, and process compatibility with low-voltage circuits. The REduced SURFace field (RESURF) technology and junction termination technology are developed to optimize the surface field of integration power devices and breakdown voltage. Furthermore, the ENhanced DIelectric layer Field (ENDIF) and REduced BULk Field (REBULF) technologies are proposed to optimize bulk fields. The double/triple RESURF technologies are further developed, and the superjunction concept is introduced to integrated power devices and to reduce the specific on-resistance. This work presents a comprehensive review of these technologies, including the innovation technologies of the authors' group, such as ENDIF and REBULF, substrate termination technology prospective integrated technologies and HVICs in wide band gap semiconductor materials are also discussed.

This article proposes the theory and implementation of an even-harmonic class-E CMOS oscillator that displays an excellent phase noise performance. Starting from zero voltage switching (ZVS) and zero derivative switching (ZDS) conditions, expressions for drain voltage and current waveforms are derived. Based on a 1:1 transformer, a custom-designed tank is proposed, which satisfies ZVS and ZDS conditions for the core transistors, provides high-Q resonances at both fundamental and second harmonics of the oscillation frequency, and yields a passive voltage gain from the drain to the gate of the core transistors. Satisfying ZVS and ZDS conditions reduces the overlap between the voltage and current waveforms of the transistor that increases the power efficiency of the oscillator. Furthermore, it widens the flat span of the semi half-sinusoidal voltage waveform, where the impulse sensitivity function (ISF) is negligible. Therefore, the conversion of the core transistor noise to phase noise is reduced. These features improve the oscillator's figure of merit (FoM) in comparison with state-of-the-art CMOS oscillators. The prototype of the even-harmonic class-E oscillator is implemented in a 0.18-μm CMOS technology. At 4 GHz, it exhibits a phase noise of -152.75 dBc/Hz at a 10-MHz offset while providing a 10.6% tuning range. The corresponding FoM is 197.9 dBc/Hz. The circuit draws 7 mA from a 0.7-V supply, and the die area is 0.23 mm².

Neurophysiological observations confirm that the brain not only is able to detect the impaired synapses (in brain damage) but also it is relatively capable of repairing faulty synapses. It has been shown that retrograde signaling by astrocytes leads to the modulation of synaptic transmission and thus bidirectional collaboration of astrocyte with nearby neurons is an important aspect of self-repairing mechanism. Specifically, the retrograde signaling via astrocyte can increase the transmission probability of the healthy synapses linked to the neuron. Motivated by these findings, in the present research, a CMOS neuromorphic circuit with self-repairing capabilities is proposed based on astrocyte signaling. In this way, the computational model of self-repairing process is hired as a basis for designing a novel analog integrated circuit in the 180-nm CMOS technology. It is illustrated that the proposed analog circuit is able to successfully recompense the damaged synapses by appropriately modifying the voltage signals of the remaining healthy synapses in the wide range of frequency. The proposed circuit occupies 7500- [Formula: see text] silicon area and its power consumption is about [Formula: see text]. This neuromorphic fault-tolerant circuit can be considered as a key candidate for future silicon neuronal systems and implementation of neurorobotic and neuro-inspired circuits.

This letter presents an ultra-compact two-stage 60-GHz differential bi-directional amplifier (DBA) design in a 65-nm CMOS process. To satisfy the stability and gain requirements, a differential neutralized bi-directional common-source gain cell combined with the cross-coupled gm-boosting technique is proposed. In addition, a layout-symmetrical coupled line transformer is used as the inter-stage matching network to achieve broadband operation, reducing insertion loss and ensuring identical responses in both forward/backward modes. The proposed DBA achieves a peak gain of 16.1 dB with a 3-dB bandwidth of 15 GHz (52-67 GHz), maximum OP $_{{1 ,,dB}}$ of 5.1 dBm, $P_{{SAT}}$ of 9.6 dBm, a peak PAE of 11.5% at 62 GHz, respectively, consuming 70 mW from a power supply of 1.2 V. The circuit core occupies an ultra-compact area of only 0.0675 mm².

Indoor visible light positioning (VLP) systems can be directly integrated with existing lighting infrastructure and achieve high-accuracy positioning when using CMOS image sensors as receivers. Due to cameras’ limited field of view (FOV), VLP systems based on multiple light emitting diodes (LEDs) require lamps to be arranged with high density, which is not practical in realistic scenarios. Additionally, smartphones held in the human hand may rotate about the x-, y- or z-axis. This paper proposes a tilted receiver camera correction method for indoor VLP systems to eliminate the additional positioning errors caused by rotation. Furthermore, the proposed method can suppress the positioning errors when part of the LED light is blocked, and can therefore enhance the robustness of the VLP system. The experimental results show that the proposed VLP method can achieve average positioning error within 7 cm when more than 40% of the LED image is captured, and can achieve average positioning error of 3.9 cm when more than 90% of the LED image is captured.

This paper presents a temperature sensor suitable for heavily duty-cycled wireless sensor node. To achieve both a fine resolution and a fast conversion time, the proposed temperature sensor embeds a RC network in a 16-bit residue-integrated successive approximation register (SAR) analog-to-digital conversion (ADC). A poly resistor is connected in series with the capacitor digital-to-analog converter (DAC) to develop a temperature-dependent ADC input. The proposed temperature sensor, implemented in 180nm CMOS, achieves a resolution of 20mK in a range of -30-to-100∘C. It shows a resolution figure-of-merit of 3pJ∙K2 while supporting a burst operation in a conversion time of 12μs after wake-up.

In this paper, we present the first CMOS SPAD with performance comparable or better than that of the best custom SPADs, to date. The SPAD-based design, fully integrated in 180 nm CMOS technology, achieves a peak PDP of 55% at 480nm with a very broad spectrum spanning from NUV to NIF and a normalized DCR of 0.2cps/m2, both at 6V of excess bias. Thanks to a dedicated CMOS pixel circuit front-end, an afterpulsing probability of about 0.1% at a dead time of3ns were achieved. We designed three SPADs with a diameter of 25, 50, and 100m to study the impact of size on the timing jitter and to create a scaling law for SPADs. For these SPADs, a SPTR of 12.1ps, 16ps, and 27ps was achieved at 6V of excess bias, respectively. The SPADs operate in a wide range of temperatures, from -65C to 40C, reaching a normalized DCR of 1.6 mcps/m2 at 6V of excess bias. The proposed SPADs are ideal for a wide range of applications, including LiDAR, super-resolution microscopy, QRNGs, QKD, fluorescence lifetime imaging, time-resolved Raman spectroscopy, to name a few.

The first stage of tactile sensing is data acquisition using tactile sensors and the sensed data is transmitted to the central unit for neuromorphic computing. The memristive crossbars were proposed to use as synapses in neuromorphic computing but device intelligence at the sensor level are not investigated in literature. We propose the concept of Transistor Memristor Sensor (TMS)-crossbar by including sensor to memristor crossbar array configuration in the input layer of the neural network architecture. 2 possible cell configurations of TMS crossbar arrays: 1 Transistor 1 Memristor 1 Sensor (1T1M1S) and 2 Transistor 1 Memristor 1 Sensor (2T1M1S) are presented. We verified the proposed TMS-crossbar in the practical design of analog neural networks based Braille character recognition system. The proposed design is verified with SPICE simulations using circuit equivalent of FLX-A501 force sensor, TiO$_2$ memristors and low power 22nm high-k CMOS transistors. The proposed analog neuromorphic computing system presents a scalable solution and is possible to encode 125 symbols with good accuracy in comparison with other Braille character recognition systems in the literature. The benefits of analog implementation of the TMS crossbar arrays is substantiated with results of accuracy, area and power requirements in comparison with the binary counterparts., Comment: 5 pages, 7 figures, TCAS2

An optical transmitter (TX) data path is demonstrated in 28-nm CMOS which drives an 850-nm vertical-cavity surface-emitting laser (VCSEL) up to 56 Gb/s non-return-to-zero (NRZ). A dc-coupled single-ended voltage-mode driver employs area- and energy-efficient equalization techniques including slew-rate-based pulse-shaping at 2x more energy- and area-efficient than optical TXs reported to date. The highly digital circuit architecture enables the supply scalability to 0.7 and 0.85 V to operate the TX at 32 and 40 Gb/s at 0.56 and 0.77 pJ/b, respectively, which is ≥ 4x more energy-efficient than the prior art.

This brief presents a class-C voltage-controlled oscillator (VCO) that ensures a robust start-up with low phase noise and high power efficiency. The proposed start-up scheme, which uses a voltage converter that operates according to the output state, relieves the start-up difficulty by supplying a timevarying bias voltage to the core transistors and allows the VCO to operate in an optimal state. The start-up circuitry is enabled only during initial operation, so power efficiency is improved without phase noise degradation. Furthermore, a capacitor array with a high quality factor is implemented by a direct capacitor connection that exhibits low series resistance. Fabricated with a 65-nm CMOS, the VCO demonstrates a frequency tuning range of 13.1% from 19.3 to 22.0 GHz. The measured minimum phase noise at a 1-MHz offset is --106.33 dBc/Hz at an oscillation frequency of 19.7 GHz, while dissipating 3.8-mW of power from a 1.0-V supply. The VCO occupies an active area of 0.064 mm2. It reveals a figureof-merit and figure-of-merit with area of --186.4 and --198.3 dBc/Hz, respectively.

This brief presents an ultra-low power low-dropout (LDO) regulator with an experimental total quiescent current consumption of only 3.08 nA. The circuit is designed to operate with a load current in the range 0 -11 mA. A novel adaptive biasing scheme based on a super source follower (SSF) structure is proposed, which measures the absolute voltage difference between the two inputs of the LDO’s error amplifier and modifies the biasing current accordingly. Thus, the transient response of the regulator is improved by counteracting the effect of using such a low bias current. The proposed LDO has been fabricated in a standard CMOS 180 nm process and the experimental characterization showed an outstanding performance in terms of maximum load current over quiescent current consumption ratio.

This paper investigates the metastability of true single-phase clock (TSPC) D flip flops (DFFs) and its impact on the resolution of Vernier time-to-digital converters (TDCs). The mechanisms of the metastability of TSPC DFFs are investigated and the analytical expressions of setup time and hold time are obtained. A shunt capacitor technique capable of reducing setup time and hold time to zero with no power and delay penalty is proposed. The impact of PVT (process, voltage, temperature) on the effectiveness of the proposed technique is quantified using simulation. Vernier TDCs, both right-shifting and left-shifting, with untuned and tuned DFFs are designed in TSMC 130 nm 1.2 V CMOS technology and analyzed using Spectre with BSIM3V3 device models. Simulation results demonstrate TDCs with tuned DFFs enjoy zero conversion error while the right-shifting and left-shifting TDCs with untuned DFFs have 1-bit and 5-bit conversion errors or 11% and 56% error rates, respectively.

A 16-bit 120 MS/s sample-hold-amplifier-less(SHA-less) pipelined analog-to-digital converter (ADC) with an on-chip calibration technique in a 0.18 μm CMOS process is presented. A switched capacitor circuit with an auxiliary unit capacitor in the multiplying-digital-to-analog converter (MDAC) of the first stage is proposed. The auxiliary-capacitor based calibration technique eliminates the need for a dedicated reference buffer to generate the calibration voltages at all the comparator thresholds. By switching the auxiliary capacitor and doing some simple calculation work, all the capacitor mismatches in the first and second stages are corrected in the digital domain, thereby significantly improving the ADC performance. Measurement results show that, with 70.1 MHz input, the signal-to-noise-and-distortion-ratio (SNDR) is improved from 75.5 dB to 77.8 dB, and the spurious-free-dynamic-range (SFDR) is improved from 81.9 dBc to 90.5 dBc with the proposed calibration technique.

Self-multiplier or square calculator design using the Vedic formulas is the new trend in quantum-dot cellular automata (QCA) technology. However, an efficient coplanar design and a complete performance analysis are still desired. This brief presents the coplanar QCA architecture of a 2-bits square calculator (proposed design-1 or PD1) using the Vedic sutra ‘Urdhva Tiryagbhyam’. Furthermore, based on the E-shaped XOR gate and majority gate (MV) an optimized architecture (proposed design-2 or PD2) is presented. The PD2 architecture exhibits notable improvement compared to the previous architecture. The proposed PD2 requires 17%, 53%, and 25% fewer cells, smaller area, and lower latency, respectively. Likewise, the extended design for 4-bits architecture (proposed design-3 or PD3) achieves 67%, 63%, and 62% superiority in cell count, covered area, and latency, respectively. Compare to the best previous design, the area-delay, QCA-specific, and energy-delay costs for PD2 (PD3) are lower by a factor of 10 ( 30), 71 ( 33), and 64 ( 83), respectively. Moreover, there is an improvement in terms of power dissipation as the QCA based designs PD2 (PD3) dissipates 1.41W10-6 mW (11.82×10-6 mW), whereas the similar type CMOS-based designs dissipate 2.29×10-2 mW (48×10-2 mW), respectively. It is worth mentioning that the comprehensive performance analyses are carried out using the QCADesigner, QCADesigner-E, and QCAPro tools.

Most analog circuits need a current reference generator to provide a stable biasing point for the transistors. Given the limited voltage headroom in advanced node technologies, there would be notable restrictions on the tolerance of the reference current deviation. Use of off-chip reference generators adds to the size of the system while the on-chip reference current generators are still partially dependent on the on-chip resistor values which is prone to technology variations. We propose an on-chip reference generator with a fully off-chip resistor which has less sensitivity to process variations. Monte-Carlo simulation results shows that the proposed has 31% more precision compared to the conventional on-chip reference generator. Measurement results in 0.18 μm CMOS shows that the chip produces a stable reference current that is defined based on an off-chip resistor. The proposed structure consumes the same current as conventional and does not add to the power consumption.

A capacitor-less (CL) low-dropout (LDO) regulator suitable to be incorporated in an on-chip system with low-voltage micro-energy-harvested supply, is proposed in this contribution. The differential input stage of the error amplifier includes bulk-driven MOS transistors, thus providing the LDO with an output voltage range that extends from the negative rail up to a level very close to the input voltage without the need of using a resistive feedback network. The circuit parameters relying on the feedback factor, β, are maximized thanks to the use of a unitary value for this parameter. The CL-LDO has been designed and fabricated in standard 180-nm CMOS technology and optimized to operate with an input voltage equal to 0.6 V and a reference level of 0.5 V. The experimental characterization of the fabricated prototypes shows that, under these operating conditions, the LDO is able to deliver a load current above 0.75 mA with a total quiescent current of only 7.0 nA. Furthermore, the proposed voltage regulator is able to operate from input voltages as low as 0.4 V, delivering in this case a maximum load current of 30 μA.

This work proposes a sequence-dependent SRAM-based PUF with enhanced reliability. It expands the CPRs by order of (rows(sequencelength+2)× columns) for reliable authentication. The proposed bitcell utilizes split word-lines to control two access transistors separately. The PUF mode turns on two left word-lines and two right word-lines simultaneously, including 18 transistors for generating one-bit data. This proposed technique supports rendering multiple data maps from one chip. Besides, various temperature and voltage combinations can create a reliability map for each data map. A test chip was fabricated in 40 nm CMOS technology. The measured worst bit error rate is 0.8% at the nominal point (1V, 20∘C). From a single chip, the proposed PUF achieved the hamming distances of 41.29% for one sequence with different orders and 44.93% for other sequences, respectively. The measured inter-chip hamming distance is 49.64.

This communication presents a differential retrodirective array (RDA) for real-time tracking. The proposed differential RDA consists of three phase-conjugating chips and two circularly polarized antenna arrays. The phase-conjugating circuit chip which is in 0.18-um CMOS process, includes a differential low-noise amplifier, a double balanced mixer and a differential power amplifier. The specifically designed chip consumes 38.4 mW with a low voltage supply of 1.2 V. Experimental results of monostatic and bistatic cases show that, the RDA has a 3-dB beamwidth up to 77°. To the best knowledgement of the authors, the proposed RDA with circular polarization, which is promising for tracking free-moving targets, is the first differential RDA enabled by specifically designed low-cost CMOS chips.

This paper presents an ultra-low power received signal strength indicator (RSSI) amplifier circuit that can be used to detect seizures through feature extraction from electroencephalography (EEG) signals. The RSSI-based feature extraction method provides a low-power area-efficient solution for analog computing based seizure detection hardware. A 6-stage RSSI amplifier circuit was designed in 65nm CMOS technology to cover the dynamic range of EEG signals with an area of 266μm×531μm. Measurement results of the RSSI circuit show that it has a power consumption of 31.6nW, covers a 45dB dynamic range, and has a linearity error of less than ±1dB.

This paper presents the design of tunable CMOS pseudo-resistors aimed at achieving large and predictable resistance values. Instrumental to the proposed pseudo-resistor is the design of current sources of extremely low currents and transistors operating in subthreshold. The effects of the leakage currents of reverse-biased pn-junctions on the pseudo-resistor resistance are also evaluated. The proposed pseudo-resistor circuit was validated while in use as part of a filter integrated in a 180 nm CMOS process. Pseudo-resistors with resistances between 180 GΩ and 700 GΩ were employed to obtain low-frequency poles of a band-pass filter adjustable from 0.6 Hz to 2 Hz.

In this article, we introduce a double-gate nanotube tunneling field-effect transistor with high scalability based on the Si/Ge heterostructure. Our device includes two Ge source regions which are covered by the gate metal to facilitate line tunneling in these regions. The tunneling charge carriers flow toward the drain region through two n⁻ Si channel regions. The manufacturing process of the proposed transistor is fully compatible with CMOS technology. The performance of the device is investigated by employing a numerical simulator which is calibrated to experimental data. We achieved a remarkable switching performance including a minimum subthreshold swing (SS) of 10 mV/dec, an I $_{{on}}$ / I $_{{off}}$ ratio of 3.92 x 10⁷, an on-state current of 52.19 μA/μm, and a drain-induced barrier lowering of 45 mV/V for the device; moreover, the ambipolar conduction completely vanished.

While MOSFET miniaturization continues to face increased challenges related to process variations, supply voltage scaling and leakage currents, exploratory devices such as Graphene Nanoribbon Field Effect Transistors (GNRFET), Tunnel Field Effect Transistor (TFET), and Carbon Nanotube Field Effects Transistors (CNFET) could provide solutions for continued device scaling with better power/performance trade-offs. The GaN TFET used in this work is a heterojunction device, where the material properties of Ga and N result in a bandgap of 3.2eV and ultra-low IOFF current. Moreover, the properties of Ga and N result in a steep-switching device with a subthreshold swing of 30mV/decade. The structure of graphene material results in high conductivity of electrons, even at very high operating temperatures, making GNRFETs a high-performance device. However, graphene specific line-edge roughness can degrade performance, and thus process related variations can have a negative impact for GNRFETs. In CNFETs, the mobility and the velocity of the conducting carriers are functions of the carbon nanotube and the gate length. The length and the diameter of the carbon nanotube material adds parasitic capacitance and resistance to the model, contributing to slower speed of the device. In this paper, the impact on power, performance, and static noise margins (SNM) of the traditional single-port 6T-SRAM and modified single-port 8T-SRAMs designed using exploratory devices are analyzed with a set figure of merit (FOM), elucidating the material properties of the devices. The results obtained from this work show that GNRFET-based SRAM have very high performance with a worst-case memory access time of 27.7 ps for a 16x4-bit 4-word array while CNFET-based SRAM bitcell consume the lowest average power during read/write simulations at 3.84 µW, while TFET- based SRAM bitcell show the best overall average and static power consumption at 4.79 µW and 57.8 pW. A comparison of these exploratory devices with FinFET and planar CMOS showed that FinFET-based SRAM bitcell consumed the lowest static power at 39.8 pW and CMOS-based SRAM had the best read, write, and hold SNMs of 201 mV, 438 mV and 413 mV respectively.

We report a miniaturized, minimally invasive high-density neural recording interface that occupies only a 1.53 mm2 footprint for hybrid integration of a flexible probe and a 256-channel integrated circuit chip. To achieve such a compact form factor, we developed a custom flip-chip bonding technique using anisotropic conductive film and analog circuit-under-pad in a tiny pitch of 75 m. To enhance signal-to-noise ratios, we applied a reference-replica topology that can provide the matched input impedance for signal and reference paths in low-noise aimpliers (LNAs). The analog front-end (AFE) consists of LNAs, buffers, programmable gain amplifiers, 10b ADCs, a reference generator, a digital controller, and serial-peripheral interfaces (SPIs). The AFE consumes 51.92 W from 1.2 V and 1.8 V supplies in an area of 0.0161 mm2 per channel, implemented in a 180 nm CMOS process. The AFE shows > 60 dB mid-band CMRR, 6.32 Vrms input-referred noise from 0.5 Hz to 10 kHz, and 48 M input impedance at 1 kHz. The fabricated AFE chip was directly flip-chip bonded with a 256-channel flexible polyimide neural probe and assembled in a tiny head-stage PCB. Full functionalities of the fabricated 256-channel interface were validated in both in vitro and in vivo experiments, demonstrating the presented hybrid neural recording interface is suitable for various neuroscience studies in the quest of large scale, miniaturized recording systems.

Radio frequency energy harvesting (RFEH) is very attractive for the Internet of things (IoT) and self-powered micro-systems such as wearable biomedical devices and wireless sensor networks. This paper proposes, analyzes, and implements a new RF-DC converter in standard 130 nm CMOS technology. The developed converter is designed and optimized for ultra-low-power IoT and wearable biomedical applications using the 900 MHz ISM band. The proposed 10-stage cross-connected rectifier compensates the transistors threshold voltage by using both dynamic and static bias compensation techniques. An analytical model of the rectifier based on the MOSFET transistor equations is presented, allowing optimization of the rectifier as a function of the number of stages and transistors sizing, improving the sensitivity and the input power range of the converter. The measurement results demonstrate a sensitivity of -25.5 dBm for 1 V output across a 5-MΩ resistive load and -29 dBm for a 100 MΩ load, which is better than the best previously reported results. The measured peak end-to-end efficiency of the proposed harvester is 42.4% at -16 dBm input power, delivering 2.19 V to a 450 kΩ load.

A novel system-on-a-chip compatible one-transistor one-capacitor ferroelectric random-access memory array (1T1C FeRAM) based on ferroelectric Hf0.5Zr0.5O2 with a capacitor under bitline (CUB) structure was experimentally demonstrated. The CUB structure facilitates the application of post-metallization annealing on metal/ferroelectric/metal capacitors above 500 °C because they are fabricated before the back-end-of-line process. A large remanent polarization of 2Pr $ {>}40~\mu \text{C}$ /cm2, projected endurance ${>}10^{11}$ cycles, and ten years of data retention at 85 °C were obtained at 500 °C, after metallization using a single large capacitor. Furthermore, a large memory window of the 64 kbit 1T1C FeRAM array with 500 °C post-metallization was comprehensively demonstrated without degradation of the underlying CMOS logic transistors. The operation voltage and speed dependence were extensively investigated using a dedicated sense amplifier for the 1T1C FeRAM. Furthermore, the perfect bit functionality at an operation voltage of 2.5 V and a read/write speed < 10 ns were obtained. Therefore, superior properties of CUB-structured 1T1C FeRAM can be achieved by flexible process engineering of crystallization annealing for metal/ferroelectric/metal fabrication.

Severe process variations in advanced technology require more devices under test (DUTs) to be characterized in the wafer acceptance test (WAT) to more reliably qualify the fabricated wafers. However, conventional WAT takes a long test time to acquire sufficient characterization data. This article proposes an on-wafer test circuity to fast and accurately characterize DUT arrays during a single probing. It integrates the proposed compact DUT cells, an IR drop compensator, and a wide-input-range (WIR) current digitizer. The proposed IR drop compensator collaborates with the DUT cells to address the IR drop issue and thus improve the test accuracy of the parameter tests. The proposed multi-mode 12-bit WIR current digitizer achieves a 140-dB input range for digitizing the DUTs' output currents in various WAT test items. It eliminates the need of high-end ATE and saves the test cost. A prototype IC including 2048 DUTs has been designed and fabricated in 90-nm CMOS. Its active area is only 60 μm by 1900 μm which can be placed in a scribe line as conventional WAT structure is. Experimental results demonstrate the proposed test circuitry can render spatial variation results and other device parameters of the DUT arrays in addition to typical WAT items.

This paper presents an ultra-lower-power (ULP) digital-to-time-converter (DTC)-assisted fractional-N all-digital phase-locked loop (ADPLL) suitable for IoT applications. A proposed hybrid time-to-digital converter (TDC) extends the vernier-TDC input range with little power overhead in order to overcome the stability issue in the conventional architectures. The hybrid TDC also facilitates a background gain calibration to achieve a stable in-band phase noise insensitive to process, voltage, and temperature (PVT) variations. The implementation of a buffer-cascaded DTC simplifies the design complexity of the fractional-N operation. The ADPLL also features a 200 μW low-phase-noise inverse-class-F (class-F⁻¹) digitally controlled oscillator (DCO) without the need of two-dimensional (2-D) capacitor tuning for frequency alignment of the fundamental and 2nd-harmonic. Fabricated in 65-nm CMOS, the ULP ADPLL prototype achieves 868 fs $ _{rms}$ jitter in a fractional-N channel when consuming only 529 μW, corresponding to a figure-of-merit (FoM) of -244 dB.

Memristors have drawn a significant widespread attention from the research community since past decade due to their high-speed operational potential in analog applications. However, it has been difficult to achieve the memristor behavior directly from solid state solution and state of the art. This work presents a novel emulator design to mimic the memristor behavior. A generic and simple emulator circuit for a voltage controlled memristor is presented using a differential difference current conveyor, which is based on a versatile second-generation current conveyor methodology. Although, the voltage-controlled memristor models are of great importance, no significant research has been done to build emulator circuits for this type of memristor. A high-speed low power DDCC in 130 nm RF-CMOS process has been designed and functional simulations have been performed on SPICE environment using Advanced Design System (Keysight Technology). Proposed DDCC then implements the memristor operation with compatible specifications. Finally, the memristor operation and potential has been verified by its application in high speed active filter operations. A universal biquad section has been presented which employs the designed memristor emulator, with 30 mW of power dissipation with ± 1.5 V supply.

Shrinking technology sizes of the CMOS circuits makes it possible to place more transistors on a single chip at each technology generation. On the other hand, circuits become more vulnerable to radiation effects due to lower supply and threshold voltage levels; thus, the number of transient faults in circuits tends to increase. Moreover, energy reduction techniques also negatively affect the reliability of circuits. Traditional high-level synthesis (HLS) methods usually consider only area and latency along with either energy or reliability. Especially the effect of using different voltage levels on reliability is completely ignored by previous studies. In this paper, we present two new HLS methods for application-specific integrated circuit (ASIC) design under area and timing constraints with the objectives of low energy consumption and high reliability. For the mapping and scheduling steps of HLS, we propose integer linear programming (ILP) and genetic algorithm (GA)-based optimization methods. While ILP provides the optimum results, the CPU time increases exponentially with the number of application nodes. On the other hand, GA-based metaheuristic is faster and determines optimum or near-optimum results in shorter times than ILP. Additionally, we use a selective duplication method to further improve the overall reliability.

This paper presents a microsystem suitable for contact-less human body temperature measurements, as well as for presence, motion and proximity detection. It consists of a 130-nm CMOS-SOI MEMS (Micro-Electro Mechanical System) thermal sensor, referred to as ``TMOS'', and its 130-nm CMOS interface circuit. The TMOS, based on a micromachined transistor, being an active device, features advantages in terms of internal gain: with optimal biasing, indeed, the TMOS achieves 274-μV/°C input-referred sensitivity at 3-cm distance and 50.33° field-of-view (FOV), outperforming thermopile detectors. The sensor and the interface circuit, featuring a chopper-stabilized-based analog readout with a 12-bit SAR ADC (Successive Approximation Register Analog-to-Digital Converter), were mounted in the same package and extensively measured: the microsystem achieves repeatability and ±0.17°C precision, thus satisfying the requirements for contact-less human body temperature measurements; furthermore, its performance as presence, motion and proximity detector was also verified.

This paper presents a switched-capacitor network (SCN) based bandgap voltage reference (BGR) for IoT applications. The proposed BGR employs a dual proportional-to-absolute-temperature (PTAT) clock topology to achieve both high precision and low power over a wide temperature range while relaxing the capacitor size requirements. Specifically, the fast PTAT clock assists in reducing the output voltage ripple of the dual-branch interleaved 2x charge pump (CP). Meanwhile, the slow PTAT clock controls the voltage divider SCN to relax the settling error at low temperature and the leakage-induced error at high temperature simultaneously, resulting in lower power consumption and smaller temperature coefficient (TC). We also propose a replica $V_{{EB}}$ generation branch in the series-parallel SCN to improve the BGR output TC due to the finite settling time during switching. Fabricated in 65nm standard CMOS, measurement results show that the proposed BGR obtains a TC of 32 ppm/°C at 0.5V supply within -40 °C to 120 °C. The line regulation is 3.3mV/V or 0.66%/V from 0.5V to 1V. Based on 10-chip measurement results, we obtain a 3σ /μ variation of 1.37% before trimming, while 0.25% after applying one-point trimming at 20°C.

Secure hardware systems are threatened by adversarial attempts on integrated circuit (IC) chips in a practical utilization environment. This article provides overviews of physical attacks on cryptographic circuits, associated vulnerabilities in an IC chip, and protection schemes in the vertical unification of systems, circuits, and packaging technologies. The design principles of on-chip monitoring circuits to sense the attackers' attempts are discussed and tested with Si demonstrators. Physical structures are explored for secure IC chips to establish protections against multimodal side-channel attacks. The backside buried metal (BBM) wirings in a Si substrate are unified with its frontside complementary metal-oxide semiconductor (CMOS) circuits to achieve avoidance, detection, and resiliency against electromagnetic and laser attacks.

Waveguide photodetectors, which convert optical signals propagating along waveguides to electrical signals, are a key building block for silicon photonic integrated circuits for communication applications. For operating in the telecom spectral band of 1.3–1.6 µm and for monolithic integration with other electronic and photonic devices on silicon platform within a single CMOS process flow, different absorbers with unique absorbing mechanisms have been developed, including epitaxial Ge-on-Si with band-to-band absorption, metallic silicide with internal photoemission absorption, and defect-assisted silicon with mid-bandgap absorption. This chapter reviews two of them, i.e., waveguide-integrated Ge-on-Si and silicide Schottky-barrier photodetectors, developed in our laboratory in terms of performances (bandwidth, responsivity, dark current, etc.), footprint, and integration process, along with the remaining technological issues and the possible solutions.

Ambipolar carbon nanotube based field-effect transistors (AP-CNFETs) exhibit unique electrical characteristics, such as tri-state operation and bi-directionality, enabling systems with complex and reconfigurable computing. In this paper, AP-CNFETs are used to design a mixed-signal machine learning logistic regression classifier. The classifier is designed in SPICE with feature size of 15 nm and operates at 250 MHz. The system is demonstrated in SPICE based on MNIST digit dataset, yielding 90% accuracy and no accuracy degradation as compared with the classification of this dataset in Python. The system also exhibits lower power consumption and smaller physical size as compared with the state-of-the-art CMOS and memristor based mixed-signal classifiers.

With helps of advancing CMOS technology, ISFETs have achieved great success. However, CMOS-based ISFETs are also suffering problems of scaling attenuation and threshold voltage offset. These problems mainly result from the architecture used to adapt standard CMOS process. To deal with these, we developed a novel CMOS ISFET configuration, namely, 3D-T-ISFET, by building a truncated architecture to expose CMOS process-inherent TiN thin film as the sensing interface. Due to the electrical conductivity of TiN, the signal from the environment can bypass the sensing dielectric and couple to the transistor effectively through the electrical double layer capacitance. Based on our experiments, as the footprint of 8.52 μm2, a 3.21-fold ΔID/pH improvement can be achieved by developed 3D-T-ISFET. At the same time, the 3D-T-ISFET has an about 1.65-fold improvement in SNR compared to the traditional 2D-ISFET. Compared to the 2D-ISFET in a state-of-the-art design, therefore, 3D-T-ISFET exhibits a scaling attenuation-free behavior and becomes less vulnerable to the non-idea effects brought by trapped charges.

A compact high-speed active quench and reset (AQR) circuit integrated with a p+/n-well single-photon avalanche diode (SPAD) is designed and fabricated in a standard 65 nm CMOS technology. The post-layout simulations showed that the quenching time for this AQR circuit is only 0.1 ns, and the smallest dead time is 3.35 ns which corresponds a maximum count rate of ~300 Mcps. The measurements showed that the SPAD pixel achieved a dark count rate of 21 kHz, a peak photon detection probability of 23.8% at a 420 nm wavelength and a timing jitter of 139 ps (using a 405 nm pulsed laser) when the excess voltage was 0.5 V. Also, due to the short quenching time, negligible afterpulsing was observed during the measurements.

A physical assessment of the lateral gate-all-around (GAA) nanosheet transistor (NSFET) at the G40M16 node (gate length = 12 nm projected for 2028) of the newly defined beyond-Moore International Roadmap for Devices and Systems [~5 nm node of the predecessor International Technology Roadmap for Semiconductors (ITRS)], supported by 3-D numerical device simulations and based on a proposed per-footprint scheme, is presented. The traditional evaluation scheme to gauge the performance of the transistor ``per effective channel width'' is shown to be improper due to pervasive bulk inversion. Bulk inversion, along the width of the nanosheet and at its ends, obfuscates the dependence of current on sheet/channel width and undermines the presumed added benefit of short-channel effect (SCE) control in the GAA device. The NSFET provides a flexible sheet width, as opposed to that of the FinFET with discrete fins, but the allowed range of sheet width is limited due to significant parasitic capacitance at a relatively narrow width and degraded SCE control and increased resistance for desired wide width. Furthermore, the nanosheet (NS) device density is undermined at a narrow width, especially for decreasing pitch. The FinFET is shown to be a favorable alternative to the NSFET even at the G40M16 node.

This article presents a $4 \times 10$ Gb/s low-noise adaptive optical receiver, utilizing a current-reuse architecture and channel crosstalk-remove techniques in 65-nm CMOS process. The receiver integrates a transimpedance amplifier (TIA), a continuous-time linear equalizer (EQ), high-gain and high-bandwidth limiting amplifiers, and a 50- $\Omega $ output driver into a single die. The TIA employs a common-source-based pseudo-differential topology with input series inductive peaking and $g_{m}$ -enhancement to improve bandwidth and noise performance. An automatic-gain-control loop scheme is presented which solves the bandwidth variation issue caused by variation of the TIA input impedance, across a large dynamic range of a small input to a maximum overload current. Multiple crosstalk reduction techniques are adopted to improve the channel isolation performance. The 850-nm vertical cavity surface emitting laser (VCSEL)-based full-link measurement results show that the optical receiver achieves $20.4~\mu \text{A}_{\mathrm {pp}}$ sensitivity bit-error-rate (BER $ -12) with a 200-fF photodiode, competitive with other prior CMOS-based TIAs. The crosstalk over different channels is also measured, demonstrating only a sensitivity penalty of 1 dB.

Cryogenic CMOS is a crucial component in building scalable quantum computers, predominantly for interface and control circuitry. Further, high-performance computing can also benefit from cryogenic boosters. This necessitates an in-depth understanding of the power and performance trade-offs in the cryogenic operation of digital logic. In this article, we analyze digital standard cells in a 28 nm high- $k$ metal gate (HKMG) CMOS foundry process design kit (PDK). We have developed Berkeley Short-channel IGFET Model (BSIM)4 of cryogenic CMOS and calibrated them with experimental measurements. Since low-temperature operation leads to an exponential decrease in the leakage current of the transistors, we further tune the threshold voltage of the devices to achieve iso-leakage. In this article, we present inverter static and dynamic characteristics and multiple ring oscillator (RO) structures. The simulation study shows that we can achieve 28% (FO4-RO) – 59% (NAND3-RO) higher performance under iso- $V_{\mathrm {DD}}$ scenario and up to 90% improvement in the energy-delay product (EDP) under iso-overdrive scenario at 6 K compared to room temperature.