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In this brief, we present a miniaturized spoof surface plasmon polaritons (SPPs) load for planar terahertz (THz) circuit application on thick substrate. The proposed SPP cell consists of a groove-shaped structure integrated with a folded stub. The coupling between the stub and the grooves enlarges the capacitance, reduces the cutoff frequency, and miniaturizes the SPP size. The strong field confinement of the SPP waveguide leads to tremendous insertion loss near the cutoff frequency. Furthermore, due to the low conductivity and high permeability, the SPP structures made of nickel (Ni) metal increase the metallic loss to 40 folds that of the aluminum (Al) case, effectively absorbing the propagating electromagnetic wave. Therefore, the tapered SPP structure made of Ni metal can operate as a load with a compact size of 1.7 λg × 0.23 λg (λg is the guided wavelength at 300 GHz). The reflection coefficient of this compact SPP load is below -20 dB in the 195 -500 GHz band. Finally, this SPP load is utilized in an equal-power two-way Goubau-line divider, with 0.194 λg substrate thickness, operating in 220-325 GHz band. The simulated and experimented results are consistent, indicating that the proposed compact SPP load could serve as a matching load for THz multiple-port circuit application on thick substrate.

In this work, we establish a comprehensive spectral model to realize effective design of high-power ytterbium-Raman fiber amplifiers (YRFAs) employing different types of Raman-pump lasers, and propose an intuitive approach for the optimization of high-power YRFAs. Quantitative comparisons with the experimental results are given in two high-power YRFAs employing Raman-pump lasers with different spectral linewidth. The consistency of measured and simulated power ratios and spectral properties of different components in the two YRFAs confirms the fidelity of the spectral model. Further theoretical analysis reveals that the impact of Raman-pump lasers on YRFAs is mainly determined by the relative intensity noise (RIN) of Raman-pump lasers up to the cutoff frequency of the pump RIN transfer function of the YRFA. Notably, the RIN of Raman-pump lasers could provide a well reference for the superior design of Raman-pump lasers in high-power YRFAs.

This paper examines the effects of temperature variation on Hetero Gate Oxide Dual Work Function Step Channel Tunnel Field-Effect Transistor (HGO-DW-SCTFET). For different temperatures, the proposed device performs better in comparison with conventional Step Channel Tunnel Field-Effect Transistor (SCTFET). This study includes a temperature-based analysis on DC and Analog parameters like drain current, threshold voltage (Vth), Sub-threshold Slope (SS), ION–IOFF ratio, trans-conductance, gate drain capacitance (Cgd), cut off frequency (fT), Trans-conductance-frequency product (TFP), Trans-conductance generation factor (TGF), Gain Bandwidth Product (GBP), Transit Time (TT) to analyze its performance at various temperatures and various models named BT-BT, SRH, and TAT, along with the linearity analysis, and the reliability of the device. The variation in DC and Analog parameters shows that the proposed device can be used for the applications of high temperature. To examine the performance of the device, a wide range of temperatures of 250K to 400K has been taken in the TCAD simulator.

This letter reports $\beta $ -(AlxGa1-x)2O3/Ga2O3 (AlGaO/GaO) heterostructure FETs (HFETs) with significant improvement of peak transconductance (g m), current and power gain cutoff frequencies. A modulation doping scheme is used to form a two dimensional electron gas in AlGaO/GaO heterostructures. Highly scaled transistors (gate lengths of 160–200 nm) were fabricated on these wafers with source/drain regrowth, scaled source access lengths and Pt Schottky gates. The fabricated HFETs show an enhancement-mode operation with high transconductance and a peak current density of 74 mA/mm. Small signal measurements show a peak current gain cut off frequency (fT) and power gain cutoff frequency (fmax) of 30 and 37 GHz respectively at 10 V drain voltage. While the cutoff frequencies are highest to date, they are limited by high source resistance at the regrowth interface. We observed a moderate off state breakdown at V GS = −2 V, limited by gate leakage and Schottky gate breakdown with an average field strength of 1.35 MV/cm. The fT.LG product 4.8 GHz- ${\mu }\text{m}$ reported for this device is higher than any other current generation $\beta $ -Ga2O3 transistors which paves the way for future RF device applications.

In the current research, for the first time, Nano-scale finger gate vacuum channel field emission transistor (FGVFET) scaling down and its limitations considering electrical characteristics are studied. The FGVFET with different cathode electrode materials, channel dimensions, and finger widths is considered and the impacts of these structural and physical changes on the key indicators of the device are assessed to achieve a comprehensive design guideline. The sensitivity analysis reveals that the channel height modification by changing gate-anode oxide and cathode–gate oxide thicknesses can be assumed as the most significant design factor in the determination of ON–OFF-state currents. The results indicate that the gate leakage current as a salient parameter in device performance is dependent on the cathode material, channel depth, and height. Furthermore, investigating cutoff frequency as the prominent factor in high-speed applications indicates that cathode–gate oxide thickness may fundamentally modify this factor.

In present work, a Linearly Graded (LG) work function is studied by considering the binary metal alloy AσB1−σ composition for the gate electrode. A high-k gate stack LG nanotube field-effect transistor (LG-NT-FET) is investigated for improving the analog performance and reduced leakage current. The present paper introduces novelty by adding charge plasma on the drain side while doping the source side in LG-NT-FET. The proposed device has the core gate, which lays inside the channel and drain area. Both the gates, including the inner and outer gates are playing a crucial role to significantly charge the channel of LG-NT-FET. It can significantly reduce the Short Channel Effects (SCEs) also. Evaluating the electrical performance metrics such as drive currents and SCEs of LG-NT-FET reveals that the proposed device can better perform in comparison with single gate silicon-based nanotube field-effect transistors (SG-NT-FETs). The device metrics get further enhanced with the tightened electrostatic control via stacking of the core-shell gate that enabled volume inversion-phase operation. The comparison of the LG-NT-FET with single gate NTFET offered a significant reduction in leakage current (~ 10− 15), rise in $${\boldsymbol{I}}_{\boldsymbol{O}\boldsymbol{N}}/{\boldsymbol{I}}_{\boldsymbol{O}\boldsymbol{F}\boldsymbol{F}}$$ ratio (~ 1013), increase in transconductance and cutoff frequency as compared to the single gate SG-NT-FET. These improvements in electrical performance metrics enable the proposed device, LG-NT-FET, as a potential device to enable CMOS scaling criteria beyond the Si-NW-FET. These improvised characteristics make LG-NT-FET a promising device in designing both digitals and analog applications for FETs.

In this work, we have examined and proposed a dielectrically modulated biosensor based on the dual trench transparent gate engineered MOSFET (DM DT GE-MOSFET) for label-free detection of biomolecules with enhanced sensitivity and efficiency. Different sensing parameters such as the ION/IOFF, threshold voltage shift have been evaluated to validate the sensing metric for the proposed device. Additionally, the SVth (Vth Sensitivity) has been also analyzed by considering the charged (positive and negative) biomolecules. In addition to this, the RF sensing parameters such as the transconductance gain and cut-off frequency have been also taken into account to provide a better insight into the sensitivity analysis of the proposed device. Furthermore, the linearity, distortion and noise immunity of the device has been evaluated to check the overall performance of the biosensor at high frequency (GHz). Moreover, the results indicate that, the proposed biosensor exhibits a SVth of 0.68 for the positively charged biomolecules at a very low drain bias (0.2 V). Therefore, the proposed device can be used as an alternative to the conventional FET-based biosensors.

Carbon nanotube field-effect transistors (CNTFETs) with optimized oxide thicknesses have been proposed. The optimum oxide thickness that provides the maximum current ratio (on/off ratio) has been calculated for each design. The effect of oxide thickness on the on/off ratio has been investigated by changing its value as the independent variable and calculating on state and off state currents. PSO algorithm has been used to find the exact optimum value of the oxide thickness with the objective of having a maximum current ratio that is one of the most important parameters in switching applications. The optimum insulator thickness is calculated for CNTFETs with different chiral vectors, insulator types, channel lengths and source/drain doping levels. For further study of the CNTFETs, performance parameters such as cutoff frequency and transconductance of the devices have also been calculated and studied. The results of the paper show that the CNTFET designers should select the oxide thickness very carefully not only based on reported values in other works. Each design requires its own optimum oxide thickness which provides the maximum on/off current ratio only for that design.

A novel slow wave (SW) substrate-integrated waveguide (SIW) with enhanced SW factor (SWF) and broadened bandwidth is proposed by simultaneously increasing the effective permeability and permittivity. The effective permittivity is increased by the enhanced capacitance between the top plane of the waveguide and the loaded patches which are shorted to the SIW bottom plane by the blind via-holes. The effective permeability is increased by lengthening the current path by adding patches on the blind via-holes. The proposed SW-SIW with simultaneous increased effective permeability and permittivity has two obvious advantages over the reported SW-SIW with only effective permeability or permittivity increased: 1) smaller longitudinal and lateral dimensions resulted from higher SWF and lower cutoff frequency, respectively, and 2) wider bandwidth due to stable wave impedance along the periodical SW structure. The lateral dimension of the proposed SW-SIW is decreased by 53% compared with the normal SIW with the same cutoff frequency. The phase velocity is decreased by 73%, which means the longitudinal length is reduced by 73% consequently. The operation band is 7.0–18.8 GHz (91.5% fractional bandwidth) covering ${X}$ - and Ku -bands. A prototype of the proposed SW-SIW is manufactured and measured, and the measured results agree well with the simulations.

A compact high-efficiency GW-level ${S}$ -band relativistic magnetron (RM) with TE11 mode output is proposed. In order to achieve high efficiency and high power, an eight-cavity slow wave system with rectangular vanes is adopted, which can provide a larger resonant system where the high-frequency energy is directly stored. All cavity axial extraction (ACAE) is applied with four 90° sector waveguides arranged azimuthally around the anode block. The four 90° sector waveguides play a significant role in converting sector waveguide TE11 mode to circular waveguide TE11 mode. The entire tube is designed without any increase in the radial dimension, which is propitious to a compact and lightweight magnet system design. In particle-in-cell (PIC) simulations, the proposed rectangular vane-type 8-cavity (R8) RM with ACAE can generate a microwave power of 2.1 GW with a pure TE11 mode at the frequency of 2.475 GHz when the applied voltage is 460 kV and the axial magnetic field is 0.46 T, and the power conversion efficiency is 68.4%.

The hybrid gate-recessed structure and ferroelectric charge trapping/storage stacked structure were used in AlGaN/GaN enhancement-mode metal–oxide–semiconductor high-electron mobility transistors (E-MOSHEMTs). The stacked structure consisted of a bottom 10-nm-thick Al2O3 tunnel oxide layer, a middle 4-nm-thick HfO2 charge trapping/storage layer, and a top 40-nm-thick LiNbO3 ferroelectric blocking layer. Using the postannealing process, a high polarized C+ domain of the pulsed laser-deposited LiNbO3 ferroelectric blocking layer was formed and the interface quality of the stacked structure was improved simultaneously. Consequently, positive threshold voltage for enhancement-mode operation was obtained. By studying the performances of the resulting devices, it was found that enhancement-mode behaviors were observed for initializing gate more than 5 V, and the threshold voltage of 1.6 V was obtained for initializing gate at 12 V. The high-frequency performances of the extrinsic unit gain cutoff frequency of 5.9 GHz and maximum oscillation frequency of 10.1 GHz were obtained. Furthermore, a low normalized noise power density of about $1.9\times 10^{-14}$ Hz−1 was achieved for the devices operating at a frequency of 10 Hz, a gate–source voltage of 5 V, and a drain–source voltage of 1 V.

Ground-penetrating radar (GPR) has been widely applied to the nondestructive inspection of concrete structures such as tunnel lining, bridge deck, and retaining wall, which are usually reinforced by steel bars. The scattering of electromagnetic (EM) waves caused by the dense steel rebar embedded in the concrete structures has a severe influence on the penetration capacity of GPR waves. In this letter, the scattering and penetration characteristics of EM waves propagating through rebar net are investigated via both numerical and laboratory experiments, with an aim to select the antenna nominal frequency for a different reinforcement density. The results show that the rebar, which is perpendicular to the polarization direction of GPR waves and has a very small diameter compared with the wavelength, is almost transparent to the impinged GPR waves. The scattering and interaction of GPR waves caused by the rebar that is parallel to the polarization direction result in a shielding effect, which is manifested as a blind band in the low-frequency range in the transmitted spectrum. This result violates the rule of thumb commonly used in the GPR community, i.e., the lower frequency has a deeper GPR penetration depth. In the end, a low cutoff frequency is recommended for selecting a GPR antenna with an appropriate nominal frequency when it is used in the detection of an anomaly inside and behind a reinforced concrete structure, in which the spacing of the rebar net is known.

In this work, we successfully used wet etching to remove the Si substrate and transferred AlGaN/GaN high-electron mobility transistor (HEMT) film with a gate length of ${2}~\mu \text{m}$ to the flexible Kapton tape. The transferred area of AlGaN/GaN epitaxial thin film reached $1.2\times1.2$ cm2. The flexible HEMTs still exhibit excellent electrical characteristics with the maximum drain current density ( ${J}_{\text {DS,max}}$ ) of 290 mA/mm and the maximum transconductance ( ${g}_{\text {m,max}}$ ) of 108 mS/mm. Furthermore, we analyzed the physical mechanisms when devices were under bending. Under bending, the tensile strain enhances the piezoelectric field within the AlGaN layer, consequently increasing the 2-D electron density. In the condition that flexible HEMTs are bent with a curvature radius of 0.3 cm, ${J}_{\text {DS,max}}$ still reaches 346 mA/mm and ${g}_{\text {m,max}}$ achieves 125 mS/mm. Besides, the main reason for the decrease in dc characteristics is verified by self-heating. As for the RF characteristics, the Si substrate removal can effectively decrease the output parasitic capacitances. Although ${g}_{\text {m,max}}$ becomes half after the transfer processes, the cutoff frequency and the maximum oscillation frequency of flexible HEMTs still reaches 3.8 and 6.5 GHz, respectively.

A differential pressure fiber optic infrasound sensor based on a mechanical filter was developed, for the detection of infrasound within the frequency range of 0.01--1 Hz. The sensing unit employs a miniature polyphenylene sulfide (PPS) diaphragm which is fixed onto a glass ferrule. An extrinsic Fabry-Perot (F-P) interferometer was fabricated between the optical fiber end face and the PPS diaphragm, and a mechanical filter structure introduced to improve the minimum detectable frequency down to 0.005 Hz. Experimental results indicate that this infrasound sensor shows a favorable frequency response for infrasound signals between 0.01 and 1 Hz, and it exhibits an average minimum detectable pressure (MDP) of 88.85 mPa·Hz−1/2. Our platform provides a promising solution for sensors in infrasound signal detection applications.

In this article, the analog/RF performance of n-channel vertically stacked gate all around (GAA) silicon nanosheet field effect transistors (Si-NSFETs) are investigated using 3-D TCAD simulations. The influence of gate length (LG) scaling, nanosheet width (WNS) and spacing between the nanosheets on the analog/RF performance of vertically stacked GAA Si-NSFET with two nanosheets are explored. The 3-D TCAD simulations indicates that reducing LG from 20 nm to 12 nm results in the improvement of RF performance in terms of increased gm (transconductance), drive current, fT (cut off frequency), fmax (maximum oscillation frequency) and degradation of analog performance in terms of reduced intrinsic gain. 3-D TCAD simulations also shows that increasing the WNS from 10 nm to 18 nm leads to the enhancement of gm and drive current, does not affect the fT and degrades the intrinsic gain due to the increase of drain conductance and gate capacitance. It is also observed that the spacing between the nanosheets does not have any significant impact on analog/RF performance of vertically stacked GAA Si-NSFETs. Consequently, the vertically stacked GAA Si-NSFETs with lower LG and higher WNS will be more suitable to realize both flash memory and dynamic random access memory (DRAM) for improved performance owing to their better RF performance.

This letter presents the design and characterization of an octave-bandwidth, small-aperture, linearly polarized, high-gain horn antenna operating in the 6–12 GHz band for active arrays. The aperture size is limited by the waveguide feed cutoff at lower frequencies and by grating lobes at higher frequencies. The radiating structure is composed of an E-plane flared horn with an exponential double ridge fed by a low-loss waveguide-to-microstrip transition, eliminating the need for additional connections between the antenna elements and the beamforming and amplification circuits. The horn is loaded with an artificial dielectric with 1 $ 2.2, which lowers the cutoff frequency and improves phase distribution over the aperture. The lens and feed loading structure are designed together to improve matching without degrading the radiation pattern. A prototype is fabricated in brass using split-block machining, and the lens is machined from 16 parallel dielectric slabs. The measured performance is in agreement with simulations.

In this article, we have demonstrated 125-nm-gate InGaAs-on-insulator (InGaAs-OI) high-electron-mobility transistors (HEMTs) on Si substrates via wafer bonding. The highlights of this device were the i-In0.53Ga0.47As/i-InAs/i-In0.53Ga0.47As quantum-well channel for high RF performance by improving electron transport properties and the low processing temperature of 250 °C or less for monolithic 3-D integration. As a result, we obtained a current gain cutoff frequency ( ${f}_{\text {T}}$ ) of 227 GHz and a maximum oscillation frequency ( ${f}_{\text {MAX}}$ ) of 187 GHz. These results are the highest ever reported in monolithic 3-D RF transistors above ${L}_{\text {G}} = {100}$ nm. In addition, through the small-signal modeling, we have found that the impact of the back-gate (BG) on RF performances of top devices is a critical issue in M3D RF systems.

An active electrode (AE) for vital signal acquisition with accurately-tunable Sub-Hz high-pass-corner frequency ( $f_{HP}$ ) has been proposed. Thanks to the proposed PVT-insensitive pseudo-resistor (PR) with embedded calibration circuit, the sub-Hz $f_{HP}$ of the AE can be accurately tuned by an external clock frequency. The AE is implemented in a standard 55nm CMOS process with a core area of 0.11 mm2. The post-layout simulation results show that up to 310 $\text{G}\Omega $ of the PR value can be achieved. Compared with the conventional PR, the variation of the calibrated PR value is reduced by 3 decades within a temperature range of 0 to 85°C under all process corners. Besides, the bootstrap technique improves the linear-input-range of the AE up to 164 mVpp, demonstrating its potential capability to be applied to recording vital signals merged with large artifacts.

In this study, intrinsic Ga2O3 (i-Ga2O3) film was deposited at about 80 K using a vapor cooling condensation system. Its bandgap energy was 5.0 eV. Low oxygen vacancy and defects were verified by using photoluminescence and Hall measurements. When a 40-nm-thick i-Ga2O3 film was used as the gate dielectric layer of AlGaN/GaN metal-oxide-semiconductor high-electron mobility transistors (MOS-HEMTs), threshold voltage, and gate breakdown voltage were − 3.5 V and − 538.0 V, respectively. The associated gate leakage current of the devices operating at a gate-source voltage of − 100 V was 0.57 μA. Furthermore, a saturation drain-source current of 186.2 mA/mm and a maximum extrinsic transconductance of 85.8 mS/mm were obtained for the devices operating at a gate-source voltage of 0 V and a drain-source voltage of 10 V. The unit gain cutoff frequency and the maximum oscillation frequency were 5.7 GHz and 11.0 GHz, respectively. The normalized noise and Hooge’s coefficient were 3.79 × 10−14 Hz−1 and 5.06 × 10−5, respectively, when the devices operated at a frequency of 100 Hz, with a drain-source voltage of 1 V and a gate-source voltage of 5 V.

We report uniform Type-II GaInAsSb/InP UTC-PDs, and compare their performance to devices fabricated with GaAsSb uniform and graded (composition and doping) absorbers of the same thickness. The quaternary UTC-PDs show a transit limited bandwidth of 274 GHz in contrast to 107 and 185 GHz for uniform and graded GaAsSb absorber UTC-PDs. Because the uniform quaternary and ternary UTC-PDs only differ in their absorber material, the findings conclusively demonstrate enhanced transport in GaInAsSb. Performance comparison to GaInAs-based devices from the literature suggest that GaInAsSb is a superior absorber material for λ = 1.55 μm high-speed photodetectors. Additionally, the external responsivity of the GaInAsSb UTC-PDs (0.094 A/W) is ~34% higher than the GaAsSb PDs (0.070 A/W). This is the first demonstration of a quaternary GaInAsSb absorber in UTC-PDs., Journal of Lightwave Technology, 39 (7), ISSN:0733-8724, ISSN:1558-2213

In this letter, high-order mode dispersion of a novel spoof surface plasmon polariton (SSPP) unit cell is reported, which has excellent bandpass propagation feature. Its asymptotic frequency and intersection frequency with light line can be independently manipulated by changing the geometric parameters of the slot in proposed SSPP unit cell. In order to validate the feasibility of high-order mode of SSPPs applied in the design of bandpass filters, two SSPP waveguides based on the method with different bandwidths are fabricated and measured. No mode-conversion transition part is introduced in the procedure of waveguide design which avoids extra addition of layout area and reduces complexity of devices. The measurements show that the proposed SSPP waveguide based on high-order mode characteristics can achieve bandpass signal propagation smoothly with controllable bandwidth.

We report the design and fabrication of a high-speed GeSn normal-incidence p-i-n photodetector. To realize high-speed detection in all telecommunication bands, we optimize the Sn content in the absorption layer, the absorption-layer thickness, and the device size. The responsivity of the 18-μm-diameter device at 1550 nm reaches 0.32 A/W with an extended cutoff wavelength of 1700 nm and a 3-dB bandwidth as high as 28 GHz under −3 V bias, clear open eye diagrams are also obtained under zero bias at 1630 nm. All the results indicate that the device has a significant potential for applications in Si-based optical telecommunication in all telecommunication bands.

This letter presents a method to convert the split dual-beam into a single one in the quasi-E-plane with low cross-polarization level for the pin-loaded fundamental EH0-mode microstrip leaky-wave antennas (MLWAs). By exciting a pair of them under differential operation with proper configuration, the ϕ -polarized dual beams can be reshaped to achieve a single-beam radiation, so as to widen its potential application. The proposed method for transversal single beam still preserves the merits of the original pin-loaded EH0-mode MLWA with simple structure and freely designed narrow width. A prototype MLWA with single-beam radiation in the quasi-E-plane is designed, fabricated, and measured. Good agreement is attained between simulated and measured results, and thus validates the unique feature of the proposed method in design of single-beam pin-loaded EH0-mode MLWAs.

In this work, ISFET frontends utilising the direct tunneling current to eliminate trapped charge are proposed. The principle has been investigated and verified via silicon-imitated ISFET first, where silicon capacitors are used to imitate the passivation ones. Because the dominant tunneling components depend on the potential difference between Gate and Drain terminals, a source-follower structure could itself perform a highpass filter with time constant at 10-100 seconds level. Additionally, a time-constant regulation mechanism is presented by feeding the output signal back to the drain terminal of ISFETs, achieving a regulation factor over 50, namely from 4.7 seconds to 243.4 seconds in our implementation. Afterwards in chemical test, proposed ISFETs have been verified in terms of unit passivation capacitance, linearity, noise and sensitivity for ISFETs with 3 different top metal areas. It is found that approximately 30.12 mV/pH sensitivity can be achieved, and for the first time we managed to derive the relation between chemical flicker noise and sensing metal area.

The gate-controlled quantum capacitance and the channel resistance play an important role in the performance of graphene field-effect transistors (GFETs). This paper experimentally verifies that the output phase of the graphene field-effect transistor changes under the influence of quantum capacitance and the channel resistance, which are controlled by the gate voltage. This phenomenon is theoretically analyzed, and a model is established to simulate the phase shift. The obtained simulation results of the model are in good agreement with the experimental results. This work reveals the influence of gate voltage variation on the phase characteristics of GFETs and provides a research basis for the application of GFETs in phase shifter and the establishment of the small-signal model.

This article presents a comprehensive study of the design and performance of a multilayer dielectric rod waveguide (MDRW) with a rectangular cross section. The design is comprised of a high permittivity core encased by a low permittivity cladding. A mathematical model is proposed to predict the fundamental mode cutoff frequency in terms of the core dimensions and the core and cladding permittivity. The model is useful for design purposes and it offers an excellent match to full-wave electromagnetic (EM) simulation results. The MDRW performance is measured for the extended Ku -band (10–18 GHz) considering straight and bent waveguides with different radius of curvatures. The particular multilayer configuration shows a 16.7% and 24% extension of the 1 dB low-band cutoff frequency for a $10\times10$ mm2 and $20\times20$ mm2 cladding area, respectively, when compared to a single layer dielectric rod waveguide (DRW) design of the same core dimensions. MDRW bends also exhibit a significant reduction of the 1 dB low-band cutoff frequency from 20% to 40% when compared to single-layer designs, for the different radius of curvature bends.

In this letter, we explore the impact of configuration parameters for Fin-like high-electron-mobility transistors (HEMTs) formed by partially etching barrier under the gate on improving transconductance (Gm) and cutoff frequency ( ${f}_{\text {T}}$ ) linearity. It is found that the Gm profile for Fin-like HEMTs can be optimized by choosing appropriate device parameters, including the etching depth ( ${H}_{\text {R}}$ ) and width ( ${W}_{\text {R}}$ ) of recess region, as well as the duty ratio ( $\alpha $ ) of the planar elements in a periodic unit along the gate width. In general, not only does ${W}_{\text {R}}$ affect the gate voltage swing (GVS) but also ${H}_{\text {R}}$ and $\alpha $ have an important role in Gm profile flatness. In addition, the fabricated Fin-like HEMTs shows a GVS of the transconductance plateau larger than 5.6 V and a constant ${f}_{\text {T}}/{f}_{\text {max}}$ of 45 GHz/65 GHz over a wide gate voltage range. Furthermore, the proposed architecture also features an exceptional linearity performance at 8 GHz with an output third-order intercept point (OIP3) of 38.5 dBm, whereas that of the planar HEMT is 31 dBm. The device demonstrated in this article has great potential to be a new paradigm for future wireless communication systems where high linearity is essential.

This paper analyzes the effect of a HfAlOx dielectric in a dual-channel (DC)single-gate (SG) metal oxide semiconductor high-electron-mobility transistor (DCSG-MOSHEMT) on improving device performance metrics. The small-signal analog/RF and noise performance of the device are explored in detail. The physics-based TCAD simulator tool is utilized to characterize the device. A peak drain current of 1.52 mA/µm is achieved due to superior sheet carrier density (ns) of 1.5×1018 cm−3 and low ON resistance. Further, a high positive threshold voltage (VT) of 0.214 V and a peak transconductance of 1.8 ms/µm is achieved with HfAlOx as the dielectric. Moreover, high cutoff frequency (fT) of 530 GHz and maximum frequency of oscillation (fmax) of 840 GHz at Vds = 0.5 V is achieved. The device exhibits a minimum noise figure of 1.32 dB at Vgs = 0.3 V and Vds = 0.5 V. With low noise over a large bandwidth and high-frequency performance, this device can be utilized to design low-noise amplifiers (LNA) for broadband applications.

In this paper, we propose dual material gate with dual-k dielectric gate oxide double gate junctionless transistor ‘DMG-DK-JLT’ for significant enhancement of performance. We showed, using 2D simulation that the proposed DMG-DK-JLT exhibit: 1) suppressed gate induced drain leakage due to band to band tunneling in OFF state (VDS = 1 V, VGS = 0 V) by 5 orders. 2) Impressively high ION/IOFF ratio of ~108. 3) For VGS=VDS = 1 V, DMG-DK-JLT performs better over conventional double gate JLT on various digital and analog performance metrics such as transconductance (Gm, 64% improvement), early voltage (VEA, 107% improvement), intrinsic gain (GmRO, 294% improvement), unity gain cutoff frequency (fT, 48% improvement), output resistance (Ro, 139% improvement), and transconductance-to-drain current ratio (Gm/ID, 218% improvement at VGS = 0.2 V, VDS = 1 V). We also compared its performance on above metrics with other gate material engineered Junctionless transistors. Moreover, we also show these values are further improved several orders by adding high-k gate sidewall spacer to our proposed DMG-DK-JLT.

In this work, we fabricated vertical organic thin film transistors (VOTFTs) with lead phthalocyanine (PbPc) as the active layer and analyzed the operating characteristics and current transfer mechanism of VOTFTs. The results show that the quiescent output current of VOTFTs is not saturated, and the output current can be modulated by requiring different gate voltages. The switching parameters of the VOTFTs are ton = 2.5 μs, toff = 3.5μs, and the switching characteristic time reaches the microsecond level. When a sine wave dynamic signal is applied to the gate electrode, the cut-off frequency fc = 77 kHz. The experimental results demonstrate that short channel and vertical structure of VOTFTs make up for organic semiconductor material defects of low carrier mobility and realize high speed and low driving voltage of organic devices. Electric field intensity of depletion layer in the gate region is 7×107V/m, and high electric field intensity makes carriers tunneling become the major transport mode. The tunnel injection model is used to analyze the carrier transport inside the transistor. The results show that the operating current of the transistor conforms to the tunneling effect theory.

Workfunction variation (WFV) in a high-k/titanium metal gate stack vertical tunnel field-effect transistor (FET) with a delta-doped layer in the germanium source is explored using technology computer-aided design simulations. The field-induced quantum confinement effect is also evaluated for the vertical tunnel FET. The impact of the gate area on various electrical parameters such as the ON-current (σION), OFF current (σIOFF), current ratio [σ(ION/IOFF)], subthreshold swing (σSS), threshold voltage (σVT), and analog performance parameters such as the total gate capacitance (σCgg), transconductance (σgm), and cutoff frequency (σfT) due to WFV of the titanium gate metal is evaluated. The results show that the variability in ION and IOFF increases when decreasing the overall transistor gate area for different metal grain sizes. In addition, the variations in the subthreshold swing and threshold voltage also decrease for a larger gate area. The distributions of the electrical parameters show that, when the grain size is comparable to the gate dimension, the distribution is not Gaussian bounded. In addition, the plot of the ratio of the average grain size to the gate area reveals that a slope of more than ~ 120 mV is attained.

Sheet beam vacuum electron tubes are an attractive solution for high-power sources or amplifiers at millimeter-wave and terahertz range. In this article, a high-order coalesced TM11-like mode operation for 220 GHz sheet beam traveling-wave tube is proposed. The feasibility of coalesced TM11-like mode operation is investigated. The utilization of high-order mode expands the RF circuit power capacity, increases the beam current and reduces the cathode emission density. The self-consistent nonlinear code and three-dimensional particle-in-cell simulations are used to verify the 6.7% beam-wave interaction at 220 GHz without phase matching optimization. The maximum output power reaches 370 W. The results demonstrate this methodology is a good solution to build a high-power device for a wide region of terahertz.

This letter presents the research progress of a pulsed G-band 50 W traveling wave tube (TWT) with pencil beam focused by periodic permanent magnet (PPM). Three approaches have been combined to improve the tube’s operation performances including setting the operating point near the cutoff frequency, using the folded waveguide (FWG) slow wave structure (SWS) with modified circular bends (MCBs), and adopting phase velocity tapering (PVT) technique. The measured output power can be over 50 W at 5% duty cycle with a bandwidth of 3.6 GHz when the beam voltage is 24.25 kV and the beam current is 59 mA. Corresponding electronic efficiency and gain are higher than 3.5% and 35 dB, respectively. The results provide a demonstration of a compact terahertz amplifier with high power, high electronic efficiency and significant bandwidth.

The most attractive application of graphene in the RF area is low-noise amplifier (LNA) due to its amazing properties. But, design and fabrication of graphene LNA Monolithic Microwave Integrated Circuits (MMICs) are still blank. In this work, 200 nm gate-length chemical vapor deposition (CVD) monolayer graphene transistors were fabricated on a sapphire substrate. The graphene transistor shows an intrinsic gain of ${g} _{\text{m}}/{g} _{\text{ds}}= {1.1}$ , and high extrinsic maximum oscillation frequency with ${f} _{\text{max}}$ (48 GHz) > cutoff frequency ${f} _{\text{T}}$ (43 GHz). The graphene transistors show low extrinsic minimum noise figure of 2–7 dB in the measured frequency range of 6–50 GHz. A C-band graphene LNA MMIC was designed and fabricated and shows a maximum gain of 8.34 dB at 5.5 GHz, and minimum noise figure of 4.96 dB at 5.8 GHz. This work demonstrates the application potential of graphene for future RF high-speed electronics.

GaN-on-Si high electron mobility transistors (HEMTs) were fabricated using Si CMOS-compatible metallization scheme for RF power amplifiers (PAs)in 5G low-power mobile system-on-chips (SoCs). Ta/Al metals were adopted for the ohmic contact formation. The device with 80-nm rectangular gate exhibited a drain current ( $I_{d\mathrm {max}}$ ) of 1.95 A/mm, a peak transconductance ( $g_{m}$ ) of 471 mS/mm, a cutoff frequency ( $f_{T}$ ) of 178 GHz, and a maximum oscillation frequency ( $f_{\mathrm {max}}$ ) of 74 GHz. At a mobile SoC-compatible supply voltage of $V_{d} = 5$ V, the device shows a peak power-added efficiency (PAE) of 51.4%/47.6%, a maximum output power density ( $P_{\mathrm {outmax}}$ ) of 1.12 W/mm/1.06 W/mm, and a gain of 16 dB/16 dB at frequency of 3.5 GHz/5 GHz, respectively. These results indicate the great potential of the GaN-on-Si HEMTs for high-performance and low-cost RF PAs for 5G mobile SoC applications.

The Switched-Resistor (S-R) approach is gaining popularity among integrated circuits designers because it allows to implement very high equivalent resistances, and thus very large time constants, in CMOS circuits. In this paper, we present an in-depth analysis of the S-R technique and propose a novel detailed model which allows to accurately predict the value of the equivalent resistance even for values of the duty cycle as low as 0.0001% which result in a huge resistance multiplication factor. We show that the conventional model of the S-R technique provides a reasonable accuracy for duty cycle values down to 1%, but its accuracy becomes unacceptable for smaller values of the duty cycle. In the proposed detailed model of the S-R we take into account also the parasitic capacitances of the integrated poly resistors and the non-ideal resistance of the CMOS switches. The modeling strategy is based on the solution of the differential equations for the different switches settings and exploits the Y-matrix to represents the floating S-R. The proposed model has been validated against periodic steady state (PSS) and periodic AC (PAC) simulations referring to a 130nm CMOS technology. Results have shown an average and maximum error lower than 0.53% and 5.15% respectively. As a further validation, a first-order active low-pass filter has been implemented with the same technology with a cutoff frequency tunable from 1.68Hz to 1.46kHz. The average and maximum errors in the estimation of the cutoff frequency have resulted lower than 3.6% and 7% respectively.

In this article, to study the features of the quadruple gate and quadruple T-gate structures in AlGaN/ GaN fin-nanochannel array metal–oxide–semiconductor high-electron-mobility transistors (MOSHEMTs), an ELS-7500 electron-beam lithography system was used to pattern the 80-nm-wide fin-nanochannel array, and the quadruple gate and quadruple T-gate structures. Compared with the conventional single-gate structure, the saturation drain–source current was improved from 1153 to 1958 mA/mm and 2009 mA/mm by using the quadruple gate structure and quadruple T-gate structure, respectively. Furthermore, the maximum extrinsic transconductance was also improved from 265 to 323 mS/mm and 340 mS/mm, respectively. Compared with the unit gain cutoff frequency ( ${f}_{T}{)}$ of 7.7 GHz and the maximum oscillation frequency ( ${f}_{{\text {max}}}{)}$ of 15.1 GHz of the conventional single gate, the ${f}_{T} = {12.0}$ GHz and ${f}_{{\text {max}}} = {18.6}$ GHz were obtained by using the quadruple gate structure. If the quadruple T-gate structure was utilized, the ${f}_{T}$ and ${f}_{{\text {max}}}$ were further improved to 14.8 and 29.5 GHz. By simulating the equivalent circuits, the improved mechanisms were attributed to the enhancement of transconductance and the reduction of parasitic gate resistance and parasitic gate capacitance.

The insulation of high-frequency transformers (HFTs) has a significant impact on the safety and reliability of high voltage power electronic transformers (PETs). The transient voltages from the rapid turn-off and turn-on of the high voltage power semiconducting device increase the insulation stress and loss, resulting in thermal stress distortion. However, few studies have presented an accurate evaluation of the dielectric loss, especially under high dV/dt square waves. This paper focuses on the dielectric loss calculation in HFT insulation by analyzing the loss from a high-frequency square wave with spike voltages. A step function that is equivalent to spike voltage superposition is proposed for the quantitative calculation of the dielectric loss of epoxy resin. A cutoff frequency ( $f_{\mathrm {c}}$ ) is defined to indicate high dV/dt characteristics. A similar narrow step function is used for simulating spike voltage at the rising/falling edge. The additional dielectric loss increases with the spike voltage and the duration. The electric field and temperature distributions are simulated in a 10 kW, 10 kHz HFT by considering the calculation of dielectric loss. The spike voltages enhance the electric field and temperature in the insulation. The increase in the external temperature (close to the glass transition temperature ( $T_{\mathrm {g}}$ ) of epoxy resin) causes a significant increase in the insulation temperature. This paper is of great importance to the design and application of HFT insulation.

This letter proposes a compact low-pass filter (LPF) using dielectric filled capacitor based on the substrate integrated suspended line (SISL) platform. A dielectric filled capacitor with high capacitance density is presented for the first time. Using this type of capacitor, a three-order lumped element LPF with a cutoff frequency of 120 MHz is designed, fabricated, and tested. The measured results agree with the simulated ones. The circuit size of the implemented SISL LPF is only $0.005\,\,\lambda \text{g}\,\,\times0.013\,\,\lambda \text{g}$ , which is very small when compared to the state of art. The measured insertion loss of SISL LPF in the passband is 0.12 dB and the stopband is from 0.35 to 2.27 GHz with a suppression level greater than 20 dB. A seven-order LPF is also designed to further demonstrate the good property of the proposed capacitor.

High-performance radio frequency (RF) switches play a critical role in allowing radio transceivers to provide access to shared resources such as antennas. They are important, especially in reconfigurable radios, where the connections within and between the different blocks (e.g., filters, amplifiers, and mixers) can be changed to customize and compose RF functions for distinct frequency bands. To realize this potential, new concepts for RF switch devices that can be integrated with standard transistor process, while providing better transmission performance, lower power consumption, smaller area, and lower actuation voltage than current RF switch technologies [e.g., field-effect transistors (FETs) and microelectromechanical systems (MEMSs)] are needed. Recently, RF switches based on emerging memory technologies, such as conductive-bridge RAM (CBRAM), resistive RAM (ReRAM), and phase-change memory (PCM), have been proposed. These nanoscale switches present major advantages, for example, high cutoff frequency, nonvolatility, fast and low-energy switching, small footprint, and compatibility with back-end-of-line (BEOL) of the standard CMOS process, thus placing them as possible contenders for high-performance RF switches. This article surveys high-performance RF switches based on resistive memories, comparing them with mature RF switching technologies like RF MEMS, p-i-n diodes, and FETs. We discuss the physical mechanisms, device structure, performance characteristics, and applications of these novel RF switches. Furthermore, we examine the prospects and future research directions of these technologies that could lead to their adoption at the industrial level.

A novel compact spoof surface plasmon polaritons (SPPs) waveguide integrated with blind vias is proposed in this brief. Depending on the groove orientation, the SPP structure leads to asymmetrical electromagnetic (EM) field confinements in the transverse plane, where the EM field is strongly confined around the groove orientation but much weaker in the opposite side. Due to this strong field confinement, the measured crosstalk between two SPP waveguides with 1 mm edge separation is −25 dB in 3–13 GHz band, a reduction of 18 dB on average when compared with microstrip line implementation. Due to the weaker field confinement, energy from the SPP waveguide can be easily coupled into other parasite structures for filter designs. By loading quarter-wavelength SPP resonators along the main SPP waveguide, we can introduce notched frequencies in the transmission. The number of notches and their frequencies can be controlled by SPP dispersion.

In this article, a new spoof surface plasmon polariton (SSPP) waveguide developed from traditional coplanar waveguide (CPW) is proposed. The asymptotic frequency of the SSPP unit cell can be easily manipulated by changing the meander groove dimensions of the SSPPs. A simple and efficient mode-conversion structure with gradient groove lengths is designed on the CPW’s ground to match the momentum of CPW to the proposed SSPPs smoothly. The designed SSPP waveguide has a good low-pass filtering property with cut-off frequency at 10.4 GHz. On this basis, another improved SSPP waveguide based on conventional grounded CPW (GCPW) is constructed, where a defected ground structure (DGS) is employed on the bottom layer of the circuit. Compared with the above work, this design has a lower cut-off frequency (8.9 GHz) and stronger field confinement. In order to validate the propagation performance, both SSPP waveguides are fabricated and measured. The measurements show that the GCPW based SSPP waveguide can effectively reduce the cut-off frequency. Such results are of great significance to the miniaturizations of plasmonic devices in microwave regime.

We present the results of low-noise silicon junction field-effect transistors (JFET) with a split-channel concept. The device can be manufactured as a module in a standard CMOS process. The channel is split under the top gate of the JFET into a source-side main channel and a drain-side-extended drain channel. Devices with design gate length between 1.0 and 3.0 $\mu \text{m}$ and effective channel length between 0.1 and 2.2 $\mu \text{m}$ were fabricated. It is shown that transconductance and channel resistance are dominated by the overlap between the main channel and the top gate. Output resistance can be enhanced by increasing the overlap of the extended drain channel with the top gate. A cutoff frequency of up to 2.5 GHz, 60-mS/mm maximum transconductance, and an intrinsic gain of 2200 were achieved. For the main channel length below ${1}~\mu \text{m}$ , a strong roll-off behavior of the threshold voltage is observed. The flicker-corner frequency for 1/f noise is 500 Hz. Above 1 kHz, a value of 2.5-nV/ ${\sqrt {\text {Hz}}}$ input-referred voltage noise density at 0.3-pF input capacitance was achieved. Also, a brief comparison to devices from other publications is presented.

Four-terminal, inline, indirectly heated phase-change switches (IPCS) have emerged as great contenders for reconfigurable radio frequency (RF) integrated circuits, providing state-of-the-art cutoff frequency thanks to their built-in dc-RF decoupling. However, the switching of IPCS devices is determined by their temperature which is challenging to predict. In this article, we present a physics-based compact model of the IPCS, validated by finite-element method simulations and measurements of IPCS devices. The model accurately predicts the thermal and electrical dynamics of the device by considering the changes in heater resistance, contact resistance, and parasitic capacitance. The complete model is implemented in Verilog-A, and a downloadable version is freely available at the nanoHUB.org. We show how the compact model can be used for rapid device evaluation and optimization between RF performance and energy efficiency. Nanosecond electrical thermometry of the heater for varying pulses during IPCS device operation and RF measurements is used to experimentally validate the model.

The $W$ -band flat-roofed sine waveguide (SWG) slow wave circuit was designed and processed in this article. Considering the limitations on present practical fabrication level, sensitivity analysis was performed on the potential influencing factors for the performance of the flat-roofed SWG slow wave structure (SWS). As indicated by the calculation results, the gap between the SWSs and the side-wall strips could have a significant impact on the dispersion, interaction impedance, and the transmission of the entire slow wave circuit. Based on the theoretical analysis, two types of $W$ -band flat-roofed SWG slow wave circuits were fabricated and tested. The side-wall strips of the two circuits are processed with/without rounded corner. The circuit without rounded corner may cause a large gap and severe reflection. In comparison, the other one with rounded corners can make the parts fit tighter, thus minimizing the potential gap. The test results demonstrate that the $W$ -band flat-roofed SWG traveling-wave tube (TWT) possesses a voltage standing wave ratio less than 1.8, which is basically consistent with the simulation results.

Rectifiers are vital electronic circuits for signal and power conversion in various smart sensor applications. The ability to process low input voltage levels, for example, from vibrational energy harvesters is a major challenge with existing passive rectifiers in printed electronics, stemming mainly from the built-in potential of the diode’s p-n-junction. To address this problem, in this work, we design, fabricate, and characterize an inkjet-printed full-wave rectifier using diode-connected electrolyte-gated thin-film transistors (EGTs). Using both experimental and simulation approaches, we investigate how the rectifier can benefit from the near-zero threshold voltage of transistors, which can be enabled by proper channel geometry setting in EGT technology. The presented circuit can be operated at 1-V input voltage, featuring a remarkably small voltage loss of 140mV and a cutoff frequency of ~300 Hz. Below the cutoff frequency, more than 2.6- $\boldsymbol \mu \text{W}$ dc power is obtained over the load resistances ranging from 5 to 20 $\text{k}\boldsymbol \Omega $ . Furthermore, experiments show that the circuit can work with an input amplitude down to 500mV. This feature makes the presented design highly suitable for a variety of energy-harvesting applications.

Wearable technologies have established novel strategies for continuous electrocardiogram (ECG) monitoring, exploiting recent developments in sensors and integrated circuit technology. Advances in dry electrodes fabrication improved the growth of wearable devices. Herein, we present an on-chip integrated ECG signal acquisition system along with dry electrodes for wearable and long-term monitoring. Custom electrodes are fabricated using multi-walled carbon nanotube (MWCNT) and Polydimethylsiloxane (PDMS) composite on a flexible substrate. A $1.5~\mu \text{W}$ fully-differential operational transconductance amplifier (OTA) with a capacitive-resistive feedback network is designed in 130 nm CMOS process achieving a mid-band gain of 43.09 dB and an input-referred noise of $2.81~\mu \text{V}_{\textit {rms}}$ in the range from 0.175 Hz to 1.636 kHz. Reconfigurability of the lower cut-off frequency is achieved by controlling the bias voltage of the triple-well nMOS transistors acting as the feedback pseudoresistor. Electrodes with different surface area and MWCNT concentrations were investigated in a real-time ECG measurement scenario. The recorded signals achieve a high signal-to-noise ratio which spans from 35.7 dB to 38.6 dB with the increasing MWCNT concentration. Experimental results demonstrate that the proposed system allows for high performance and low-power ECG signal recording for the long-term and wearable applications.

Nanosheet gate-all-around transistors are analyzed for RF applications using calibrated TCAD simulations. The effects of stack spacing and number of stacks on device performance are studied and a substack design for improved RF performance is proposed. The novel substack design can improve cut-off frequency ( ${F}_{{t}}$ ) by ~10% and minimum number of substacks and minimum substack spacing should be used.

A novel slow wave structure (SWS), named staggered double corrugated waveguide (SDCW), is proposed for the development of wideband high-power terahertz (THz) traveling wave tubes (TWTs). The SDCW-SWS not only has the wideband characteristic of staggered double grating (SDG) but also has the high interaction impedance characteristic of symmetrical double grating. In addition, its tunnel width is independent of the lower cutoff frequency and can be further increased. Numerical Eigen mode calculations show that, under the same dispersion, the passband of SDCW-SWS is increased by more than 10 GHz compared with SDG-SWS, and the average interaction impedance at 195 GHz is increased by about 62%. A particle-in-cell simulation analysis confirms that the average output power, saturated gain, and electron efficiency of SDCW-TWT at 195 GHz are ~110 W, ~20.34 dB, and ~5.46%, respectively, when the operating voltage is 20 kV and the beam current is 100 mA. Therefore, SDCW is a promising slow wave circuit of wideband high-power THz traveling wave amplifier.

In this paper, we propose and simulate a lateral asymmetrically doped channel-based tunnel field-effect transistor. The impact of laterally asymmetric channel (LAC) on the performance of a Tunnel F...