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The metallization grid pattern is one of the most important design elements for high-efficiency solar cells. This paper presents a model based on the unit cell approach to accurately quantify the power losses of a specialized interdigitated metallization scheme for polycrystalline silicon thin-film solar cells on glass superstrates. The sum of the power losses can be minimized to produce an optimized grid-pattern design for a cell with specific parameters. The model is simulated with the standard parameters of a polycrystalline silicon solar cell, and areas for efficiency improvements are identified, namely, a reduction in emitter finger widths and a shift toward series-interconnected, high-voltage modules with very small cell sizes. Using the model to optimize future grid-pattern designs, higher cell and module efficiencies of such devices can be achieved.

A pMOS transistor can be used as an electrostatic discharge (ESD) protection device; however, due to its higher turn-on resistance, it has a poor ESD robustness than that of nMOS transistors. Nevertheless, for a high-voltage (HV) p-channel laterally-diffused MOS (pLDMOS), which has a low impact-ionization rate, almost a non-snapback phenomenon (high V h value) and then with a high latch-up (LU) immunity. What is happening if a pLDMOS embedded with an HV silicon-controlled rectifier (ESCR)? In this paper, a novel HV pLDMOS-ESCR is proposed by implanted an extra N+ diffusion region in the drain-side among a pLDMOS. Meanwhile, the location of the N+ diffusion region is changed in order to investigate the impact on ESD capability. And, in this work, three different unit finger widths will be evaluated. Eventually, the I t2 value of “pnp”-type among HV pMOS-ESCR will be four times higher than that of “npn”-type at least, in the same time, the V h value of “pnp”-type HVpMOS-ESCR higher than that of “npn”-type, too. Therefore, the “pnp”-type HV pLDMOS-ESCR structure is an excellent structure in the HV technology due to its high ESD and latch-up immunities.

In this paper we present an approach to achieve both 100 mg paste deposit on a c-Si solar cell and efficiency gains with no impact on peel strength at extremely narrow finger widths. Using the double print process with suitable pastes and screens we demonstrate an 0.18% absolute efficiency gain and 20% paste saving over the standard process. This benefit is correlated to the finger width reduction from 63 μm to 47 μm, leading to an increase in Isc and Voc, due to the reduced recombination area under the metal contacts. The peel strength is also shown to increase from 1.5 N to 3 N for the same busbar thickness, when different paste compositions for the DP process are used. We also show screen lifetimes above 30k prints in production, with a stable process in terms of efficiency gain and paste saving.

Experimental results are presented on the magnetostatic-surface wave (MSSW) scattering properties of a grating of metal fingers placed at a variable height above the YIG film and compared with theory. The agreement with theory is excellent if one takes into account energy storage at the metal-finger edges and if the width of the metal fingers is larger than the YIG-film thickness. It is concluded that, for smaller finger widths, the interaction between the edges of a metal finger must additionally be incorporated into the theory. The present results are significantly different from those for the scattering of magnetostatic forward volume waves (MSFVW's) by a grating of metal fingers. In the latter case, the scattered modes are propagating MSFVW's so that the problem of interaction between the edges of metal fingers is not present, i.e., the theory is valid for all widths of the metal fingers.