Search

This letter provides an overview of the metal-embedded chiplet assembly for microwave integrated circuits (MECAMICs) technology. MECAMIC is a 2.5-D wafer-level packaging approach that provides seamless heterogeneous integration capabilities of compound semiconductor transistors (e.g., GaN HEMTs) with passive components and interconnects using a backside metal embedding process. The chiplets are embedded in through-interposer cavities, and the backside metallization locks the chiplets into position while providing dc and RF ground for the high-frequency circuits. With this hybrid manufacturing approach, high-performance RF ICs can: 1) be designed using the best transistor technology for the function; 2) be fabricated in short cycle times through hybrid manufacturing; and 3) compete performancewise with monolithic circuits. We demonstrated an $X$ -band power amplifier circuit realized in MECAMIC with a saturated output power of 31 dB and a peak power added efficiency of 54%, which compared favorably to its monolithic GaN monolithic microwave integrated circuit (MMIC) counterpart. The MECAMIC process cycle time was $4.5\times $ faster than the monolithic process.

We describe our recent results in developing and maturing small pixel (5μm pitch), high definition (HD) mid-wave infrared (MWIR) detector technology as well as focal-plane-array (FPA) hybrids, and prototype 2.4 Megapixel camera development operating at high temperature with low dark current and high operability. Advances in detector performance over the last several years have enabled III-V high operating temperature (T≥150K), unipolar detectors to emerge as an attractive alternative to HgCdTe detectors. The relative ease of processing the materials into large-format, small-pitch FPAs offers a cost-effective solution for tactical imaging applications in the MWIR band. In addition, small pixel detector technology enables a reduction in size of the system components, from the detector and ROIC chips to the focal length of the optics and lens size, resulting in an overall compactness of the sensor package, cooling and associated electronics. An MBE system has been used to grow antimony-based detector structures with 5.1μm cutoff with low total thickness variation (TTV) across a 3” wafer, in order to realize high interconnect yield for small-pitch FPAs. A unique indium bump scheme is proposed to realize 5μm pitch arrays with high connectivity yield. Several 1kx2k /5μm hybrids have been fabricated using Cyan’s CS3 ROICs with proper backend processing and finally packaged into a portable Dewar camera. The FPA radiometric result is showing low median dark current of 2.3x10 -5 A/cm 2 with > 99.9% operability, and >60% QE (without AR coating).

We report very wideband 100 MHz to 1 GHz active circulator with high power operation up to 30 dBm for the first time. In order to achieve broadband high power circulation and isolation, a new architecture is developed using low-loss RF choke concept and it is implemented on alumina substrate with mounted GaN HEMT devices along with other SMTs. The performed test shows minimum 15 to 20 dB isolation up to 30 dBm and 15 dB directivity up to 26 dBm across the band with 2.5~5 dB insertion loss for 15 dB of minimum directivity.

A high azimuth and elevation resolution multiple-input-multiple-output(MIMO) radar prototype with 16 Tx and 16 Rx antenna elements was developed in this work to address the autonomous driving vehicle challenges in complex urban environments. This article describes the technological scope of the developed prototype, details the performance challenges and discusses the system design considerations. The main goal of the developed automotive radar prototype is to achieve a high 2D angular resolution in the presence of a large number of radar echoes while maintaining an industry acceptable antenna aperture size and reasonable cost.

A 10-GHz filter/receiver module is implemented in a novel 3-D integration technique suitable for RF and microwave circuits. The receiver designed and fabricated in a commercial 0.18-mu m CMOS process is integrated with embedded passive components fabricated on a high-resistivity Si substrate using a recently developed self-aligned wafer-level integration technology. Integration with the filter is achieved through bonding a high-Q evanescent-mode cavity filter onto the silicon wafer using screen printable conductive epoxy. With adjustment of the input matching of the receiver integrated circuit by the embedded passives fabricated on the Si substrate, the return loss, conversion gain, and noise figure of the front-end receiver are improved. At RF frequency of 10.3 GHz and with an IF frequency of 50 MHz, the integrated front-end system achieves a conversion gain of 19 dB, and an overall noise figure of 10 dB. A fully integrated filter/receiver on an Si substrate that operates at microwave frequencies is demonstrated.

This paper presents a polymer-based wafer-level integration technology suitable for integrating RF and mixed-signal circuits and systems. In this technology, disparate dies can be integrated together using a batch fabrication process. Very high density die-to-die interconnects with widths currently as small as 25 mum are implemented. To demonstrate the capabilities of this technology, a 10-GHz receiver front-end implemented in 0.18-mum CMOS technology is integrated with a high-resistivity Si substrate and embedded passives. By adjusting the input matching of the receiver using the embedded passives fabricated on the high-resistivity Si substrate, the input matching and conversion gain of the front-end receiver are improved

InAsSb material with a cutoff wavelength in the 5 μm range has been grown on GaAs substrates. The MWIR InAsSb detector arrays were fabricated and hybridized to a ROIC to permit measurement of the electrical and optical properties of detectors. Detector arrays were fabricated in a 1024 x 1024 format on an 18 μm pitch. A fanout was utilized to directly acquire data from a set of selected detectors without an intervening read out integrating circuit (ROIC). Variable temperature Jdark vs Vd measurements have been made with the dark current density ~ 10-5 A/cm 2 at 150 K. The external QE measured using a narrow band filter centered at ~ 4 μm had values in the 65 – 70 % range. Since the detectors were illuminated through a GaAs substrate, which has a reflectance of 29%, the internal QE is greater than 90%. A 1024 x 1024 ROIC on an 18 μm pitch was also designed and fabricated to interface with the barrier detectors. The ROIC operates at 30 Hz frame rate and has a well capacity of 20.7 M electrons. QE at 150 K for a 1024 x 1024 detector array hybridized to a ROIC had a median D* at 150 K under a flux of 1.07 x 1015 ph/(cm 2 /s) was 1.2 x 1011 cm Hz1/2 /W. The NEdT was 44 mK and imagery was obtained at 150 K using an f/2.3 MWIR lens.

InAsSb material with a cutoff wavelength in the 5 μm range has been grown on GaAs substrates. The MWIR InAsSb detector arrays were fabricated and hybridized to fanouts and ROICs to permit measurement of the electrical and optical properties of detectors. Detector arrays were fabricated in a 1024 x 1024 format on an 18 μm pitch. A fanout was utilized to directly acquire data from a set of selected detectors without an intervening read out integrating circuit (ROIC). Variable temperature Jdark vs Vd measurements have been made with the dark current density ~ 10 -5 A/cm 2 at 150 K. The external QE measured using a narrow band filter centered at ~ 4 μm had values in the 65 - 70 % range. Since the detectors were illuminated through a GaAs substrate which has a reflectance of 29%, the internal QE is greater than 90 %. A 1024 x 1024 ROIC on an 18 μm pitch was also designed and fabricated to interface with the barrier detectors. The ROIC operates at 30 Hz frame rate and has a well capacity of 20.7 M electrons. QE at 150 K for a 1024 x 1024 detector array hybridized to a ROIC had a median D* at 150 K under a flux of 1.07 x 10 15 ph/(cm 2 /s was 1.2 x 10 11 cm Hz 1/2 /W. The NEdT was 44 mK and imagery was obtained at 150 K using an f/2.3 MWIR lens.

In InAs1-xSbx material alloy composition was adjusted to achieve 200K cutoff wavelengths in the 5 mm range. Reflectance was minimized and absorption in the InAs1-xSbx material maximized by the use of pyramid shaped structures fabricated in the InAs1-xSbx material which function as an AR coating. Compound-barrier (CB) detectors were fabricated and tested for optical response and dark current density versus bias measurements were acquired as a function of temperature. For 5 mm cutoff detectors, QE is high, ~ 75 % between 4.0 mm and 4.6 mm and g 80 % between 2.0 mand 4.0 mm, demonstrating the efficacy of the pyramids as photon trap structures and as a replacement for multi-layer AR-coatings. Jdark in the low 10-3 A/cm2 range at 200 K and low 10-5 A/cm2 range at 150 K was measured at the bias at which the QE peaked.© (2012) COPYRIGHT Society of Photo-Optical Instrumentation Engineers (SPIE). Downloading of the abstract is permitted for personal use only.

parylene-N is used as a dielectric layer to create ultra low-loss 3-D vertical interconnects and coplanar waveguide (CPW) transmission lines on a CMOS substrate. Insertion loss of 0.013 dB for a 3-D vertical interconnect through a 15- m-thick parylene-N layer and 0.56 dB/mm for a 50- CPW line on the parylene-N layer (compared to 1.85 dB/mm on a standard CMOS substrate) are measured at 40 GHz. L-shaped, U-shaped, and T-junction CPW structures are also fabricated with underpasses that eliminate the discontinuities arisen from the slot-line mode and are characterized up to 40 GHz. A 3-D low-noise amplifier using these post-processed structures on a 0.13- m CMOS technology is also presented along with the investigation of parasitic effects for accurate simulation of such a 3-D circuit. The 3-D circuit implementation reduces the attenuation per unit length of the transmission lines, while preserving the CMOS chip area (in this specific design) by approximately 25%. The 3-D amplifier measures a gain of 13 dB at 2 GHz with 3-dB bandwidth of 500 MHz, noise figure of 3.3 dB, and output 1-dB compression point of + 4.6 dBm. Room-temperature processing, simple fabrication, low-loss performance, and compatibility with the CMOS process make this technology a suitable choice for future 3-D CMOS and BiCMOS monolithic microwave integrated circuit applications that currently suffer from high substrate loss and crosstalk.

Coplanar waveguide transmission lines and vertical interconnects are implemented on a thick (15µm) Parylene-N dielectric layer over a lossy CMOS-grade Si substrate. Devices are measured up to 40GHz and show very low loss behavior. Low loss tangent and low dielectric constant characteristics of Parylene-N result in significant improvement of transmission lines and interconnects compared to those implemented in a standard Si integrated circuit technology.

A modification to a recently developed chip/wafer integration technology has proven to be very effective in suppressing the substrate crosstalk for mixed signal systems. In this implementation, analog and digital chips are fabricated on separate dies, and then integrated on a single Si substrate using a Self-Aligned Wafer-Level Integration Technology. A truly grounded faraday-cage structure is realized by sidewall metallization around each die resulting in an ultimate substrate noise reduction. Any planar chip with any thickness can be used in this technology. Simulation and measurement results show that when a high - resistivity silicon substrate as an integration medium is used along with grounded faraday cage, substrate coupling is suppressed to less than -60 dB for frequencies up to 25 GHz. For a low-resistivity silicon substrate, the substrate coupling is a dominant mechanism in generating mixed-signal noise, however, when sidewall metallization as faraday cage is utilized, the substrate coupling is reduced by at least 20 dB for frequencies below 25 GHz. The substrate noise suppression is higher than 35 dB for frequencies below 2 GHz. To our knowledge, these are the best values reported for isolation improvement of thick silicon substrates at microwave frequencies.

In this work Parylene-N is investigated as a passivation layer for microwave and millimeter-wave integrated circuits (MMIC). The electrical and mechanical properties of this material show great potential for various applications in integrated circuits especially at higher frequencies. For the first time, Parylene-N has been used as a passivation layer on different test structures and their performance is studied up to 40GHz. The measurement results obtained from ring resonators and Coplanar Waveguide (CPW) transmission lines before and after passivation show that a 10 μm thick Parylene-N layer increases the insertion loss by only a negligible amount (0.007dB/mm at 40GHz), while a 5 μm thick coating does not have any influence on the insertion loss, confirming that the loss tangent of this coating material is very low. Besides, in measuring the resonance frequencies of different ring resonators a frequency shift of less than 1% is observed with a 10 μm passivation at 40GHz, while the shift is less than 0.05% for a 5 μm thickness, indicating a very low dielectric constant. In this paper we also show the performance of a multi-layer structure using a Coplanar Waveguide (CPW) vertical transition with vias etched between two Parylene-N layers. The results demonstrate the ability to use this flexible material as a low loss multi-layer substrate for microwave frequency applications. Finally a humidity study is performed by employing an array of dewpoint sensors with 10 μm thick Parylene-N coating. Hence the Mean Time to Failure (MTTF) under different humidity and temperature conditions is derived. Results indicate that Parylene-N is a good candidate as an encapsulant for MMIC applications.