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Memristor, one of the fundamental circuit elements, has promising applications in non-volatile memory and storage technology as it can theoretically achieve infinite states. Information can be stored independently in these states and retrieved whenever required. In this paper, we have proposed a non volatile memory cell based on memristor emulator. The circuit is able to perform read and write operations. In this memristor based memroy cell, unipolar pulse is used for writing and bipolar pulse is used for reading. Unlike other earlier designs, the circuit does not need external read/write enable switches to switch between read and write operations; the switching is achieved by the zero average bipolar read pulse given after the completion of write cycle. In our proposed memristor based memory cell, single bit can be read and any voltages from 0 to 5 volts can be written. Mathematical analysis and the simulation results of memristor emulator based read write circuit have been presented to confirm its operation.

This paper presents an in-depth and rigorous mathematical analysis of a family of nonlinear dynamical circuits whose only nonlinear component is a Chua Corsage Memristor (CCM) characterized by an explicit seven-segment piecewise-linear equation. When connected across an external circuit powered by a DC battery, or a sinusoidal voltage source, the resulting circuits are shown to exhibit four asymptotically stable equilibrium points, a unique stable limit cycle spawn from a supercritical Hopf bifurcation along with three static attractors, four coexisting dynamic attractors of an associated non-autonomous nonlinear differential equation, and four corresponding coexistingpinched hysteresis loops. Thebasin of attractions of the above static and dynamic attractors is derived numerically via global nonlinear analysis. When driven by a battery, the resulting CCM circuit exhibits a contiguous fixed-point loci, along with its DC V–I curve described analytically by two explicit parametric equations. We also proved the fundamental feature of theedge of chaos property; namely, it is possible to destabilize a stable circuit (i.e., without oscillation) and make it oscillate, by merely adding a passive circuit element, namely $$L >0$$. The CCM circuit family is one of the few known example of a strongly nonlinear dynamical system that is endowed with numerous coexisting static and dynamic attractors that can be studied both experimentally, and mathematically, via exact formulas.

Nonlinear memristor-based neural network and a circuit-based learning system is addressed in this work. The weights of the neural network are based on the memristor bridge synapse and the learning architecture is designed in analog–digital mixed circuits by adopting a simple learning algorithm called random weight change algorithm. Though the memristor bridge can be efficiently used as a synapse, it still suffers from nonlinearity in weight programming at its extremes due to the boundary effect of memristors, which is a common phenomenon in most of the nano-devices. In this study, a novel architecture of a modified memristor bridge synapse is proposed that avoids the boundary effect issue by shifting the programming origin to the middle of the linear region. To demonstrate the effectiveness of the proposed method, multilayer neural network along with the end-to-end learning architecture is designed in circuit with nonlinear memristors and tested for several classical learning problems. Simulation results showing successful learning and correct behavior of replicated neural network are presented.

In this paper, we propose a complex neuro-memristive synapse that exhibits the physiological acts of synaptic potentiation and depression of the human-brain. Specifically, the proposed neuromorphic synapse efficiently imitates the synaptic plasticity, especially long-term potentiation (LTP) and depression (LTD), and short-term facilitation (STF) and depression (STD), phenomena of a biological synapse. Similar to biological synapse, the short- or long-term potentiation (STF and LTP) or depression (STD or LTD) of the memristive synapse are distinguished on the basis of time or repetition of input cycles. The proposed synapse is also designed to exhibit the effect of reuptake and neurotransmitters diffusion processes of a bio-synapse. In addition, it exhibits the distinct bio-realistic attributes, i.e., strong stimulation, exponentially decaying conductance trace of synapse, and voltage dependent synaptic responses, of a neuron. The neuro-memristive synapse is designed in SPICE and its bio-realistic functionalities are demonstrated via various simulations.

Memristors represent the fourth electrical circuit element complementing resistors, capacitors and inductors. Hallmarks of memristive behavior include pinched and frequency-dependent I–V hysteresis loops and most importantly a functional dependence of the magnetic flux passing through an ideal memristor on its electrical charge. Microtubules (MTs), cylindrical protein polymers composed of tubulin dimers are key components of the cytoskeleton. They have been shown to increase solution’s ionic conductance and re-orient in the presence of electric fields. It has been hypothesized that MTs also possess intrinsic capacitive and inductive properties, leading to transistor-like behavior. Here, we show a theoretical basis and experimental support for the assertion that MTs under specific circumstances behave consistently with the definition of a memristor. Their biophysical properties lead to pinched hysteretic current–voltage dependence as well a classic dependence of magnetic flux on electric charge. Based on the information about the structure of MTs we provide an estimate of their memristance. We discuss its significance for biology, especially neuroscience, and potential for nanotechnology applications.

This article reviews the nonlinear dynamical attributes, switching kinetics, bifurcation analysis, and physical realization of a family of generic memristors, namely, Chua corsage memristors (CCM). CCM family contains three 1-st order generic memristor dubbed as 2-lobe, 4-lobe, and 6-lobe Chua corsage memristors and can be distinguished in accordance with their asymptotic stable states. The 2-lobe CCM has two asymptotically stable equilibrium states and regarded as a binary memory device. In contrast, the versatile 4-lobe CCM and 6-lobe CCM are regarded as a multi-bit-per-cell memory device as they exhibit three and four asymptotic stable states, respectively, on their complex and diversified dynamic routes. Due to the diversified dynamic routes, the CC memristors exhibit a highly nonlinear DC V-I curve. Unlike most published highly-nonlinear DC V-I curves with several disconnected branches, the DC V-I curves of CCMs are contiguous along with a locally active negative slope region. Moreover, the DC V-I curves and parametric representations of the CCMs are explicitly analytical. Switching kinetics of the CCM family can be demonstrated with universal formulas of exponential state trajectories xn(t), time period tfn, and applied minimum pulse amplitude VA and width Δw. These formulas are regarded universal as they can be applied to any piecewise linear dynamic routes for any DC or pulse input and with any number of segments. When local activity, and bifurcation and chaos theorems are employed, CMMs exhibit unique stable limit cycles spawn from a supercritical Hopf bifurcation along with static attractors. In addition, the nonlinear circuit and system theoretic approach is applied to explain the asymptotic stability behavior of CCMs and to design real memristor emulators using off-the-shelf circuit components.

In this paper we propose a new first-order generic memristor, namely, a 4-lobe Chua corsage memristor, as an extension of the 2-lobe Chua corsage memristor. The newly designed corsage memristor exhibits more complex dynamical routes with three stable equilibrium points for which it reveals a higher degree of versatility that the dynamic route changes in response to a change in initial conditions. One of the most important feature of our new memristor is its contiguous DC V-I curve. In contrast, most published highly-nonlinear DC V-I curves have several disconnected branches. Moreover, in this paper, we exploit the properties of the 4-lobe Chua corsage memristor to design an oscillator by connecting the memristor in series with an inductor and a battery. The resulting circuit oscillates about a locallyactive operating point located on the negative slope region of the memristor?s DC V-I curve. We investigate the local activity, edge of chaos, and Hopf bifurcation phenomena and carry out an in-depth analysis of the nonlinear dynamics of the oscillation in our oscillator circuit.

In this paper, a memristive artificial neural circuit imitating the excitatory chemical synaptic transmission of biological synapse is designed. The proposed memristor-based neural circuit exhibits synaptic plasticity, one of the important neurochemical foundations for learning and memory, which is demonstrated via the efficient imitation of short-term facilitation and long-term potentiation. Moreover, the memristive artificial circuit also mimics the distinct biological attributes of strong stimulation and deficient synthesis of neurotransmitters. The proposed artificial neural model is designed in SPICE, and the biological functionalities are demonstrated via various simulations. The simulation results obtained with the proposed artificial synapse are similar to the biological features of chemical synaptic transmission and synaptic plasticity.

This paper presents a circuit-theoretic foundation of the “memristor,” and clarifies why it is fundamentally different from a 3-terminal device with a similarly-sounding name called the “memistor.” Here we show that while the memristor is a basic 2-terminal circuit element based on classic nonlinear circuit theory, the memistor is an ad hoc 3-terminal gadget devised for one specific application, and does not qualify as a 3-terminal circuit element because it is impossible to predict its behavior when connected with other circuit elements.

Memristor is a new circuit element defined by a state-dependent Ohm’s law between the memristor voltage and current. It has recently been successfully built, however, its electrical characteristics are not fully known yet. Like other circuit elements R, L and C, there could have various configurations of multiple memristors including serial and parallel connections in a variety of applications. When input voltage/current is supplied to a circuit with multiple memristors, behavior of the device becomes complicated and is difficult to predict. In this chapter, composite characteristics of the serial and parallel connections of memristors are investigated using both linear and nonlinear models. Also, the behavior of individual memristor is formulated mathematically and a general computation method of composite memristance for multiple memristor circuits of diverse configurations is proposed.

A novel generic memristor, dubbed the 6-lobe Chua corsage memristor, is proposed with its nonlinear dynamical analysis and physical realization. The proposed corsage memristor contains four asymptotically stable equilibrium points on its complex and diversified dynamic routes which reveals a 4-state nonlinear memory device. The higher degree of versatility of its dynamic routes reveal that the proposed memristor has a variety of dynamic paths in response to different initial conditions and exhibits a highly nonlinear contiguous DC V-I curve. The DC V-I curve of the proposed memristor is endowed with an explicit analytical parametric representation. Moreover, the derived three formulas, exponential trajectories of state xnt, time period tfn, and minimum pulse amplitude VA, are required to analyze the movement of the state trajectories on the piecewise linear (PWL) dynamic route map (DRM) of the corsage memristor. These formulas are universal, that is, applicable to any PWL DRM curves for any DC or pulse input and with any number of segments. Nonlinear dynamics and circuit and system theoretic approach are employed to explain the asymptotic quad-stable behavior of the proposed corsage memristor and to design a novel real memristor emulator using off-the-shelf circuit components.

A floating type of memristor emulator which acts like the behavior of memristor has been developed. Most of existing memristor emulators are grounded type which is built disregarding the connectivity with other memristor or other devices. The developed memristor emulator is a floating type whose output does not need to be grounded. Therefore, the emulator is able to be connected with other devices and be utilized for the interoperability test with various other circuits. To prove the floating function of the proposed memristor emulator, a Wheatstone bridge is built by connecting 4 memristor emulators in series and parallel. Also this bridge circuit suggest that it is possible to weight calculation of the neural network synapse.

Implementation of memristor-based multilayer neural networks and their hardware-based learning architecture is investigated in this paper. Two major functions of neural networks which should be embedded in synapses are programmable memory and analog multiplication. "Memristor", which is a newly developed device, has two such major functions in it. In this paper, multilayer neural networks are implemented with memristors. A Random Weight Change algorithm is adopted and implemented in circuits for its learning. Its hardware-based learning on neural networks is two orders faster than its software counterpart.

Memristor is a new kind of memory device whose resistance varies depending upon applied charge and whose previous resistance state is preserved even when its power is off. Ordinary memristor has a nonlinear programming characteristics about time when a constant voltage is applied. For the easiness of programming, it is desirable that resistance is programmed linearly about time. We had proposed previously a memristor bridge configuration with which weight can be programmed nicely in positive, negative or zero. In memristor bridge circuit, two memristors are connected in series with different polarity. Memristors are complementary each other and it follows that the memristance variation is linear with respect to time. In this paper, the linearization effect of weight programming of memristor bridge synapse is investigated and verified about both memristor from HP and a nonlinear memristor with a window function. Memristor bridge circuit would be helpful to conduct synaptic weight programming.

In this paper, a generic model of memristive systems, which can emulate the behavior of real memristive devices is proposed. Non-ideal pinched hysteresis loops are sometimes observed in real memristive devices. For example, the hysteresis loops may deviate from the origin over a broad range of amplitude A and frequency f of the input signal. This deviation from the ideal case is often caused by parasitic circuit elements exhibited by real memristive devices. In this paper, we propose a generic memristive circuit model by adding four parasitic circuit elements, namely, a small capacitance, a small inductance, a small DC current source, and a small DC voltage source, to the memristive device. The adequacy of this model is verified experimentally and numerically with two thermistors (NTC and PTC) memristors.

Memristor-based circuit architecture for multilayer neural networks is proposed. It is a first of its kind demonstrating successful circuit-based learning for multilayer neural network built with memristors. Though back-propagation algorithm is a powerful learning scheme for multilayer neural networks, its hardware implementation is very difficult due to complexities of the neural synapses and the operations involved in the learning algorithm. In this paper, the circuit of a multilayer neural network is designed with memristor bridge synapses and the learning is realized with a simple learning algorithm called Random Weight Change (RWC). Though RWC algorithm requires more iterations than back-propagation algorithm, we show that a circuit-based learning using RWC is two orders faster than its software counterpart. The method to build a multilayer neural network using memristor bridge synapses and a circuit-based learning architecture of RWC algorithm is proposed. Comparison between software-based and memristor circuit-based learning are presented via simulations.

Emulations of memristor-family elements are very important, since their physical realizations are very difficult to achieve with recent technologies. Although some previous studies succeeded in designing memristor and memcapacitor emulators, no significant contribution towards meminductor emulator has been presented so far. The implementation of a meminductor emulator is very important, since real meminductors are not expected to appear in near future. We designed the first meminductor emulator whose inductance can be varied by an external current source without employing any memrisitve system. The principle of our architecture and its feasibility have been verified using SPICE simulation.

This paper presents a simple oscillator using a battery and a second order memristor without the energy storage elements inductor and capacitor. The oscillating mechanism of the proposed circuit has been explained via Hopf bifurcation theorem, small signal model, local activity principle and edge of chaos theorem. This paper can be also used as a reference for explaining the intimate relationship between the super-critical Hopf bifurcation phenomenon and the edge of chaos.

A mutator-based meminductor emulator whose inductance can be varied by an external current source is proposed. The implementation of a meminductor emulator is very important, since real meminductors are not physically realizable with current technology. Though there is active research on memristor or memcapacitor emulators, no significant contribution for the meminductor emulator has been presented yet. In this paper, a meminductor emulator has been built using the principle of a mutator, in that a memristor with $$v-i$$ v - i at one port functions as a meminductor in the other port, whose input is characterized by $$\varphi - i$$ ? - i curve. It is shown that multiple meminductor circuits can be built in various configurations with memristors combined with a single mutator. The feasibility of our meminductor emulator and its expandable configurations are verified experimentally and SPICE simulation.

This exposition shows that the potassium ion-channels and the sodium ion-channels that are distributed over the entire length of the axons of our neurons are in fact locally-active memristors. In particular, they exhibit all of the fingerprints of memristors, including the characteristic pinched hysteresis Lissajous figures in the voltage-current plane, whose loop areas shrink as the frequency of the periodic excitation signal increases. Moreover, the pinched hysteresis loops for the potassium ion-channel memristor, and the sodium ion-channel memristor, from the Hodgkin-Huxley axon circuit model are unique for each periodic excitation signal. An in-depth circuit-theoretic analysis and characterizations of these two classic biological memristors are presented via their small-signal memristive equivalent circuits, their frequency response, and their Nyquist plots. Just as the Hodgkin-Huxley circuit model has stood the test of time, its constituent potassium ion-channel and sodium ion-channel memristors are destined to be classic examples of locally-active memristors in future textbooks on circuit theory and bio-physics.

This paper illustrates that for a device to be a memristor it should exhibit three characteristic fingerprints: 1) When driven by a bipolar periodic signal the device must exhibit a “pinched hysteresis loop” in the voltage-current plane, assuming the response is periodic. 2) Starting from some critical frequency, the hysteresis lobe area should decrease monotonically as the excitation frequency increases, and 3) the pinched hysteresis loop should shrink to a single-valued function when the frequency tends to infinity. Examples of memristors exhibiting these three fingerprints, along with non-memristors exhibiting only a subset of these fingerprints are also presented. In addition, two different types of pinched hysteresis loops; the transversal (self-crossing) and the non-transversal (tangential) loops exhibited by memristors are also discussed with its identification criterion.

Composite characteristics of the parallel and serial connections of memristors are investigated. The memristor is one of the fundamental electrical elements, which has recently been successfully built. However, its electrical characteristics are not yet fully understood. When multiple memristors are connected to each other, the composite behavior of the devices becomes complicated and is difficult to predict, due to the polarity dependent nonlinear variation in the memristance of individual memristors. In this work, we investigate the relationships among flux, charge, and memristance of diverse composite memristors, using both linear and nonlinear memristor models, and analyze the characteristics of complex memristor circuits.

A charge-bouncing solution to avoid the undesirable drift in a programmed memory during readout of a memristor-based non-volatile memory is proposed. A memristor memory can be programmed by using strong programming signals, and the programmed memristance can be readout by using weak readout signals. Though readout signals are weak compared to programming signals, the readout charge accumulates over time, leading to an undesirable drift of the operating point. This causes an error in the programmed memory. Memristance drift is an important problem for practical utilization of memristors as memories. The only way presented so far to avoid such a drift is by converting input signals to doublets, but non-ideal doublet signals still cause drift problems. In the proposed method, drift is avoided using a capacitor in such a way that all the charge injected into the memristor during readout is stored in the capacitor and bounced back through the memristor after the readout has been completed. Experimental results showing an excellent recovery from the temporal memristance drift when using singlet pulses rather than the conventionally-used doublet pulses for memristive memory readout are also presented.

A linearized programming method of memristor-based neural weights is proposed. Memristor is known as an ideal element to implement a neural synapse due to its embedded functions of analog memory and analog multiplication. Its resistance variation with a voltage input is generally a nonlinear function of time. Linearization of memristance variation about time is very important for the easiness of memristor programming. In this paper, a method utilizing an anti-serial architecture for linear programming is proposed. The anti-serial architecture is composed of two memristors with opposite polarities. It linearizes the variation of memristance due to complimentary actions of two memristors. For programming a memristor, additional memristor with opposite polarity is employed. The linearization effect of weight programming of an anti-serial architecture is investigated and memristor bridge synapse which is built with two sets of anti-serial memristor architecture is taken as an application example of the proposed method. Simulations are performed with memristors of both linear drift model and nonlinear model.

A memristor emulator which imitates the behavior of a TiO2 memristor is presented. Our emulator is built from off-the-shelf solid state components. To develop real world memristor circuit applications, the emulator can be used for breadboard experiments in real time. Two or more memristor emulators can be connected in serial, in parallel, or in hybrid (serial and parallel combined) with identical or opposite polarities. With a simple change of connection, each memristor emulator can be switched between a decremental configuration or an incremental configuration. The hardware and spice simulation of the proposed emulator showed promising results that provides an alternative solution of hp TiO2 memristor model in real circuit.

Analog hardware architecture of a memristor bridge synapse-based multilayer neural network and its learning scheme is proposed. The use of memristor bridge synapse in the proposed architecture solves one of the major problems, regarding nonvolatile weight storage in analog neural network implementations. To compensate for the spatial nonuniformity and nonideal response of the memristor bridge synapse, a modified chip-in-the-loop learning scheme suitable for the proposed neural network architecture is also proposed. In the proposed method, the initial learning is conducted in software, and the behavior of the software-trained network is learned by the hardware network by learning each of the single-layered neurons of the network independently. The forward calculation of the single-layered neuron learning is implemented on circuit hardware, and followed by a weight updating phase assisted by a host computer. Unlike conventional chip-in-the-loop learning, the need for the readout of synaptic weights for calculating weight updates in each epoch is eliminated by virtue of the memristor bridge synapse and the proposed learning scheme. The hardware architecture along with the successful implementation of proposed learning on a three-bit parity network, and on a car detection network is also presented.

In this paper, we propose a memristor bridge circuit consisting of four identical memristors that is able to perform zero, negative, and positive synaptic weightings. Together with three additional transistors, the memristor bridge weighting circuit is able to perform synaptic operation for neural cells. It is compact as both weighting and weight programming are performed in a memristor bridge synapse. It is power efficient, since the operation is based on pulsed input signals. Its input terminals are utilized commonly for applying both weight programming and weight processing signals via time sharing. In this paper, features of the memristor bridge synapses are investigated using the TiO memristor model via simulations.

A memristor bridge neural circuit which is able to perform signed synaptic weighting was proposed in our previous study, where the synaptic operation was verified via software simulation of the mathematical model of the HP memristor. This study is an extension of the previous work advancing toward the circuit implementation where the architecture of the memristor bridge synapse is built with memristor emulator circuits. In addition, a simple neural network which performs both synaptic weighting and summation is built by combining memristor emulators-based synapses and differential amplifier circuits. The feasibility of the memristor bridge neural circuit is verified via SPICE simulations.

A pulse-based programmable memristor circuit for implementing synaptic weights for artificial neural networks is proposed. In the memristor weighting circuit, both positive and negative multiplications are performed via a charge-dependent Ohm's law (). The circuit is composed of five memristors with bridge-like connections and operates like an artificial synapse with pulse-based processing and adjustability. The sign switching pulses, weight setting pulses and synaptic processing pulses are applied through a shared input terminal. Simulations are done with both linear memristor and window-based nonlinear memristor models.

A method to design a Cellular Neural Network architecture using memristors is proposed. Memsitor is a new resistive device whose resistivity varies depending upon applied voltage/current. In this paper, we show that a memristor bridge circuit consisting of four identical memristors that is able to perform zero, negative and positive synaptic weightings. Together with three additional transistors, the memristor bridge weighting circuit is able to perform synaptic operation for neural cells. Also, we show that Cellular Neural Networks can be implemented with the programming of different set of weights on the memristor bridge synapses.

Error is the major problem in communication system. Absolute circuit is one of the most important building blocks to implement for the error measurement in communication system as well as in analog circuit design. The main goal of this paper is to design a circuit with high accuracy and minimum error performance. In this paper, a new current mode absolute circuit is implemented to calculate the absolute value of two signals. This new design shows enhanced performance and low distortion over the previous implementation. The proposed circuit is simulated using Hspice and implemented in analog viterbi decoder. It is very suitable for implementing in error calculation for the large scale integrated circuit. Hspice simulation results of previous and new one circuit are reported.

The memristance variation of a single memristor with voltage input is generally a nonlinear function of time. Linearization of memristance variation about time is very important for the easiness of memristor programming. In this paper, a method utilizing an anti-serial architecture for linear programming is addressed. The anti-serial architecture is composed of two memristors with opposite polarities. It linearizes the variation of memristance by virtue of complimentary actions of two memristors. For programming a memristor, additional memristor with opposite polarity is employed. The linearization effect of weight programming of an anti-serial architecture is investigated and memristor bridge synapse which is built with two sets of anti-serial memristor architecture is taken as an application example of the proposed method.

The cellular-neural-network universal machine (CNN-UM) technique which performs analog addition/subtraction between image frames has been developed. The equivalent circuit of the uncoupled CNN without self feedback is reduced to a simple RC circuit. If two inputs are presented to the circuit one after another during a very short time period, the voltages that are proportional to their input signals are superimposed on the state capacitor. The output of such superimposition is a reduced version of the addition/subtraction between the two signals. Simple amplification of the output can recover the actual output. The characteristics of analog addition/subtraction with the proposed algorithm are shown via on-chip experiment. Application of the proposed algorithm to moving target detection is also presented.

A high speed target detection and tracking algorithm for a CNN-UM chip is presented in this paper. The target confidence value is computed based on the fusion of target existence probabilities of features using products of weighted sums. The target decision is done with such a confidence value and target initiation is done through the temporal accumulation of the confidence. The probability of the target existence for each feature is created in the region of influence depending on the reliability and the strength of the feature. By virtue of the analogic parallel processing structure of the CNN-UM (Roska T, Chua LO. The CNN universal machine: an analogic array computer. IEEE Trans. Circuits Systems II 1993; CAS-40: 163–173), real time tracking can be achieved with presently available technologies with the speed of several kilo-frames per second. Due to the utilization of multiple features of target, robust target detection is possible via the proposed algorithm. On-chip experiments of the proposed target-tracking algorithm have been done and properties of the proposed approach are disclosed through the various experiments. Copyright © 2003 John Wiley & Sons, Ltd.

This paper presents a detailed analysis of various oscillatory behaviors observed in relation to the calcium and potassium ions in the third-order Morris–Lecar model of giant barnacle muscle fiber. Since, both the calcium and potassium ions exhibit all of the characteristics of memristor fingerprints, we claim that the time-varying calcium and potassium ions in the third-order Morris–Lecar model are actually time-invariant calcium and potassium memristors in the third-order memristive Morris–Lecar model. We confirmed the existence of a small unstable limit cycle oscillation in both the second-order and the third-order Morris–Lecar model by numerically calculating the basin of attraction of the asymptotically stable equilibrium point associated with two subcritical Hopf bifurcation points. We also describe a comprehensive analysis of the generation of oscillations in third-order memristive Morris–Lecar model via small-signal circuit analysis and a subcritical Hopf bifurcation phenomenon.

The Chua Corsage Memristor is the simplest example of a passive but locally active memristor endowed with two asymptotically stable equilibrium points [Formula: see text] and [Formula: see text] when powered by an E-volt battery, where [Formula: see text]. The basin of attraction is defined by [Formula: see text], [Formula: see text] for [Formula: see text], and [Formula: see text], [Formula: see text] for [Formula: see text]. By adding an inductor of appropriate value [Formula: see text] in series with the battery, the resulting circuit undergoes a supercritical Hopf bifurcation and becomes an oscillator for [Formula: see text]. Applying a sinusoidal voltage source [Formula: see text] across the Chua corsage memristor, one finds two distinct coexisting stable periodic responses, depicted by their associated pinched hysteresis loops, of the same frequency [Formula: see text] whose basin of attraction is defined by [Formula: see text], and [Formula: see text], respectively, where [Formula: see text] depends on both amplitude A and frequency f. An in-depth and comprehensive analysis of the above global nonlinear phenomena is presented using tools from nonlinear circuit theory, such as Chua’s dynamic route method, and from nonlinear dynamics, such as phase portrait analysis and bifurcation theory.

In this paper, we present a device to be a memristor should exhibit three characteristic fingerprints: (a) Pinched hysteresis loop in the voltage v vs. current i plane, namely, the v-i loci always passes through origin for any bipolar periodic input voltage v(t). (b) Beyond a certain critical frequency ω*, the area of the pinched hysteresis lobe decreases monotonically as the frequency of the periodic input signal increases and (c) the shape of the pinched hysteresis loop varies with frequency f and shrinks to a single-valued function through the origin, as the frequency tends to infinity. Examples of memristors exhibiting these three fingerprints are presented.

A circuit with multiple memristors can have various configurations including serial and parallel connections like R, L and C. When input voltage/current is supplied to a circuit with multiple memristors, the composite behavior of the memristor circuit goes through a transition state period before it enters a steady state period. During the transient state period, the behavior is very complex and not predictable due to each memristor's different action depending upon its connection polarity and initial state. In this paper, the transient characteristics of a composite memristor are analyzed via the relationships of charge, flux and memristance of each memristor.

When multiple memristors are connected to each other, the composite behavior of the devices becomes complicated and is difficult to predict, due to the polarity dependent nonlinear variation in the memristance of individual memristor. In this paper, we investigate the relationships among flux, charge and memristance of diverse composite memristors, using the HP TiO2 model, and analyze the characteristics of complex memristor circuits. It is assumed that all memristor circuits operate at a stable composite memristance state, in which the composite flux curve does not vary and the memristor circuits act as a single memristive system, regardless of input current or voltage. Such study will be conducted for serial and parallel memristor circuits.

An electronic oscillator circuit is designed by connecting an inductor in series with a locally-active PTC Memristor and a battery. The PTC Memristor is locally active on the negative resistance region of its DC [Formula: see text]–[Formula: see text] curve. A DC operating point [Formula: see text] is chosen on the locally-active region of the PTC Memristor and a small-signal equivalent circuit at [Formula: see text] is derived via Taylor series. The small-signal admittance [Formula: see text] of the composite one-port in Fig. 1 is derived using the small-signal equivalent circuit at [Formula: see text], in series with an inductor whose value is chosen such that [Formula: see text] at some [Formula: see text]. The sinusoidal oscillation computed numerically from this circuit is shown to emerge from a supercritical Hopf bifurcation.

This paper demonstrates that the Chua Corsage Memristor, when connected in series with an inductor and a battery, oscillates about a locally-active operating point located on the memristor’s DC [Formula: see text]–[Formula: see text] curve. On the operating point, a small-signal equivalent circuit is derived via a Taylor series expansion. The small-signal admittance [Formula: see text] is derived from the small-signal equivalent circuit and the value of inductance is determined at a frequency where the real part of the admittance [Formula: see text] of the small-signal equivalent circuit of Chua Corsage Memristor is zero. Oscillation of the circuit is analyzed via an in-depth application of the theory of Local Activity, Edge of Chaos and the Hopf-bifurcation.

The generation of action potentials (oscillations) in biological systems is a complex, yet poorly understood nonlinear dynamical phenomenon involving ions. This paper reveals that the time-varying calcium ion and the time-varying potassium ion, which are essential for generating action potentials in Barnacle giant muscle fibers are in fact generic memristors in the perspective of electrical circuit theory. We will show that these two ions exhibit all the fingerprints of memristors from the equations of the Morris–Lecar model of the Barnacle giant muscle fibers. This paper also gives a textbook reference to understand the difference between memristor and nonlinear resistor via analysis of the potassium ion-channel memristor and calcium ion-channel nonlinear resistor. We will also present a comprehensive in-depth analysis of the generation of action potentials (oscillations) in memristive Morris–Lecar model using small-signal circuit model and the Hopf bifurcation theorem.

A memristor emulator circuit which is designed with off-the-shelf solid state components is presented. As the memristors are not commercially available so far, some circuit replacements which behave like memristors are needed to develop application circuits. In this paper, the variable resistance of a memristor is built utilizing the input resistance of the closed loop circuit of an OP amp. The memristor emulator circuit has been implemented on breadboard with off-the-shelf solid state components. The experimental results of the proposed memristor emulator circuit show a memristor behavior that can be utilized as an alternative of hp TiO2 memristor model.

A simple and compact memristor-based bridge circuit which is able to perform signed synaptic weighting in neuron cells is proposed. The proposed memristor-based synapse is composed of four memristors which makes a bridge type configuration. By programming different values on each memristor of the memristor bridge circuit, weighting values can be set on the memristor bridge synapses. Various simulation results are included.

This paper presents a memristor based new synaptic circuit, consisting of five memristor in a bridge structure together with one differential amplifier. The circuit is able to perform positive and negative weighting for pulse type inputs in neural cells. Processing is conducted with applied pulses at a common terminal in different time slots. It is compact, non-volatile and low power efficient. Simulations of sign setting, weight setting and synaptic multiplication are performed with hp TiO 2 memristor models.

We present an application-specific integrated circuit (ASIC) CMOS chip that implements a synchronized oscillator cellular neural network with a matrix size of 32 × 32 for object sensing and labeling in binary images. Networks of synchronized oscillators are a recently developed tool for image segmentation and analysis. Its parallel network operation is based on a “temporary correlation” theory that attempts to describe scene recognition as if performed by the human brain. The synchronized oscillations of neuron groups attract a person’s attention if he or she is focused on a coherent stimulus (image object). For more than one perceived stimulus, these synchronized patterns switch in time between different neuron groups, thus forming temporal maps that code several features of the analyzed scene. In this paper, a new oscillator circuit based on a mathematical model is proposed, and the network architecture and chip functional blocks are presented and discussed. The proposed chip is implemented in AMIS 0.35 μm C035M-D 5M/1P technology. An application of the proposed network chip for the segmentation of insulin-producing pancreatic islets in magnetic resonance liver images is presented.

Reconfigurability and flexibility are often desired characteristics in an automatic system whose capability needs to be changed from time to time to meet the need of its operation. In this study, a Hardware Description Language (HDL) software core for joint torques/forces computation for an n-joint general purpose manipulator is designed. This HDL core can be used in a reconfigurable robot control design. The inverse dynamics computation determines required joint torques for creating desired accelerations. Our study results in a state machine with forty-seven states. A complete torque computation can be finished in 167 clock cycles in microseconds if Xilinx XC2V4000 Field Programmable Gate Array (FPGA) device is used. This manipulator-structure independent core design can be integrated with other components on FPGAs. There could be a significant reduction in the load on the microprocessor by shifting heavy-load computation to FPGAs.