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The reliability evaluation of logic circuits is an essential step in the computer-aided design flow of emerging integrated circuits (IC). Due to the increased process variation effects in submicron IC technologies, reliability evaluation should include the transistor-level faults’ modeling and analysis. In this paper, a two-step reliability evaluation method was developed. In the first step, the gate error probability (in a matrix form) was computed based on transistor fault modeling. In the second step, the circuit’s graph was traversed in topological order. Meanwhile, for each gate, the probability of the gate’s output to be in 16 possible states was computed using the gate error probability matrix (calculated in the first step) and the corresponding gate inputs’ probability matrices. The reliability of the circuit’s outputs was extracted from the related 16-state probability matrix. Furthermore, the reconvergent fan-out problem was handled using the concept of correlation coefficients. Various simulations were performed on ISCAS 89 and LGSynth91 benchmark circuits. Compared with MonteCarlo as a reference method, the results indicated a

Two-level inverter is extensively used in photovoltaic micro-grid power generation system. The transistor in the two-level inverter works under high stress and is prone to failure. In order to increase the practicability and reliability of photovoltaic micro-grid system inverters, it is necessary to study a fast and accurate fault diagnosis method for inverters. Therefore, this paper proposes a new open-circuit fault diagnosis method for photovoltaic micro-grid inverter. The proposed method has a simple calculation process and only needs to analyze the output current without the use of additional sensors, so the diagnosis cost is low. According to the different changes of output current, the diagnostic variables and adaptive thresholds are calculated for fault diagnosis and location. It can be seen from the simulation report that this method can diagnose the fault of transistor quickly and accurately, and it is robust to load disturbance.

This paper addresses the methods to retain the functionality of the soft-switching current-fed converter in the case of transistor fault. Various primary-side transistor faults and corresponding scenarios to minimize the influence on the converter characteristics are presented. The proposed method allows preserving the power delivery and converter soft-switching operation in the case of fault of one of the primary side transistors. Post-fault operation was experimentally verified using a 500W converter prototype, and resulting implications for converter efficiency were analyzed.

Renewable energy sources become an increasing alternative power source. Among the available energy sources, Photovoltaic (PV) has a remarkable growth and a significant penetration in many applications. PV-based power supplies are managed by switching power converters and the connected activities will halt when power supply fails. In this paper, we propose an original fault tolerant cascaded step-up step-down converter circuit, under transistor fault. Both open-circuit fault (OCF) and short-circuit fault (SCF) of transistors are considered. The fault tolerant operation of the proposed circuit is based on the following elements: fault tolerant cascaded step-up step-down circuit, transistor fault diagnosis and suitable reconfigurable control. The originality of the proposed fault tolerant circuit lays on implementing a global reconfiguration for the two-cascaded stages, based on a single synchronous redundant transistor. Moreover, the fault detection is based on the waveforms of the inductance currents. An efficient reconfigurable control with fast post-fault management is also proposed. Some selected simulation results are provided to validate the effectiveness of the fault tolerant operation.

A novel fast open-transistor diagnosis approach for voltage-source inverters (VSI) based on calculated bridge arm pole-to-pole (PTP) voltages is proposed in this paper. The theoretical PTP voltages can be calculated with duty cycle ratio and DC input, and the real PTP voltages can be calculated with output voltages and currents. When no fault occurs, there should be no difference between the theoretical and the real PTP voltages. Once fault happens, great deviations between these two calculated voltages will be incurred and can be utilized to detect and localize the fault. This method is able to achieve fast diagnosing speed, while no extra hardware circuits and complex calculation are needed, thus it can be embedded in the existing control system with little effort. Furthermore, strong robustness against operation variation makes this method feasible in diversified applications. Simulations and experiments have been carried out to validate the correctness and effectiveness of this method.

The number of power semiconductor switches and DC sources will increase with the increase in the number of levels of output voltage of the multilevel inverter. As the number of power semiconductor switches increases, the possibility of its failure and hence the breakdown of the inverter operation also escalate in a nonlinear manner. Hence, the detection of the failure of the power semiconductor switch is of paramount importance, considering the availability and reliability of the system is concerned. The gate unavailability or the transistor open circuit fault detection in asymmetrical multilevel inverter by means of monitoring the mean value of the output voltage is presented in this paper. Simulation of this method is carried out in both binary and trinary combinations of asymmetric multilevel inverter.

To meet increasing demand for higher reliability in power electronics converters applicable in electric vehicles, fault detection (FD) is an important part of the control algorithm. In this study, a model-based open transistor fault diagnsosis method is presented for a voltage-source inverter (VSI) supplying a five-phase permanent magnet motor drive. To realise this goal, a model-based observer is designed to estimate model parameters. After that, the estimated parameters are used to design a sliding mode observer in order to estimate the phase current in an ideal model. Subsequently, the proposed FD technique measures the similarity between the estimated current and real current using cross-correlation factor. This factor is used for the first time in this study to define a FD index in VSI. The presented FD scheme is simple and fast; also, it is able to detect multiple open switch or open phase faults in contrast to conventional methods. On the other side, in order to track reference current of the motor, the estimated parameters are used to design a proportional resonant controller. The FD technique is used to operate a multiphase fault-tolerant brushless direct current (BLDC) motor drive. Experimental results on a five-phase BLDC motor with in-wheel outer rotor applicable in electrical vehicles are conducted to validate the theory.

In this paper a transistor open-circuit fault diagnosis problem in two-level voltage inverter controlled shunt active power filter drives was discussed. Taking into consideration requirements of the contemporary monitoring drive systems original transistor fault diagnostic technique were proposed. Presented results were obtained by designed in PSIM software simulation model.

A new fault model that incorporates both logic and circuit level description is presented. The model, called Logic Transistor Function (LTF), is developed to represent nMOS combinational circuits. The LTF uncovers extensive information about the structure of the circuit, and is utilized to specify the output of the fault-free and faulty circuits with single or multiple transistor stuck faults. The LTF is effective in modelling the sequential behaviour of the faulty combinational nMOS circuit. A procedure that relies on the LTF model is introduced to detect classical and non-classical faults. The circuit is tested by first partitioning the nMOS circuit and then obtaining the primitive D-cubes of the faulty partition. A variant of the D-algorithm may be applied to accomplish detection. The procedure is systematic, thus making it attractive for programming.

To advance the field of electronics prognostics, the study of transistor fault modes and their precursors is essential. This paper reports on a platform for the aging, characterization, and scenario simulation of gate controlled power transistors. The platform supports thermal cycling, dielectric over-voltage, acute/chronic thermal stress, current overstress and application specific scenario simulation. In addition, the platform supports in-situ transistor state monitoring, including measurements of the steady-state voltages and currents, measurements of electrical transient response, measurement of thermal transients, and extrapolated semiconductor impedances, all conducted at varying gate and drain voltage levels. The aging and characterization platform consists of an acquisition and aging hardware system, an agile software architecture for experiment control and a collection of industry developed test equipment.

A novel method is presented for the detection and isolation of open-transistor faults in voltage-source inverters feeding low-power AC motors. The method is based on monitoring two diagnostic signals, one indicating sustained near-zero values of output current and thus permitting fault detection, the other permitting the isolation of the particular transistor which went faulty. The latter signal is the ratio of the average phase current and the average magnitude thereof. The method proves to work reliably, enabling detection and isolation of all possible cases of single and multiple faults. It enjoys high immunity to transients and noise and requires no extra hardware on top of that normally used for basic control purposes.

Fault diagnosis of electrical drives is becoming more and more important today, since variable speed drives have become industrial standard in many applications. As an integral part of the drive, many faults occur within the inverter. One possible fault within the inverter is an open circuit transistor fault, whose diagnosis is subject of this paper. The practical performances of several open-circuit fault diagnostic methods are tested in simulation and experiment. An overview of the different strategies is given, including the algorithms used to localize the open transistor. Simulation results are presented and show different capabilities of each diagnostic strategy in terms of effectivity and false alarm resistivity for a voltage source inverter used as an active rectifier. The existing methods are further developed and adapted to a closed loop controlled active rectifier. An experimental setup in the laboratory is used to validate simulation results. Typical detection results are presented including time-to-detection measurements.

Recently, we have introduced a comprehensive model for detecting single and multiple faults for MOS combinational circuits based on the logic transistor function concept. In this paper, we extend our previous work to cover MOS combinational circuits that have multiple output lines. A new algorithm is developed which is used to generate test vectors that are capable of detecting single and multiple stuck faults in multiple output MOS combinational circuits. We also introduce a new concept where all the transistors in a specific circuit are realized into a number of transistor sets which alleviates the analysis and planning of a test strategy that accommodates a particular test requirement, i.e. detecting a certain transistor fault occurrence, or fits particular test restrictions, i.e. output line limitation. The advantages of this concept in design for testability is outlined. The relationship of fault coverage and output lines is also introduced and analysed.

An application of the D-algorithm in generating tests for MOS circuit faults is described. The MOS circuits considered are combinational and acyclic but may contain transmission gates and buses. Tests are generated for both the stuck type faults and the transistor faults (open and short). A logic model is derived for the MOS circuits. In addition to the conventional logic gates, a new type of modeling block is used to represent the "memory" state caused by the "open" transistors. Every fault, whether a stuck type fault or a transistor fault, is represented in the model as a stuck fault at a certain gate input. For generating tests, however, the D-algorithm needs modification. The singular cover and the D-cubes for the new gate include some memory states. To handle the memory state, an initialization procedure has been added to the consistency part of the D-algorithm. The procedure of modeling and test generation is finally extended to transmission gates and buses.

The problem of testing differential cascode voltage switch (DCVS) circuits is analyzed. These circuits have several potential applications in fault-tolerant, highly available system design due to their inherent self-checking capability. It is shown how concurrent (online) testing of DCVS circuits, which is very effective under single transistor fault assumptions, can be performed. The impact of multiple faults of DCVS circuits is examined, and analytical results are derived. These results indicate that periodic offline tests on DCVS circuits are necessary in order to achieve high multiple-fault coverage. Single-fault test sets and/or pseudorandom vectors were successfully used in the offline tests to detect many of the multiple faults which reduce the efficiency of online tests. The results show the need for a comprehensive mixed-test strategy combining offline and online tests for DCVS circuits. >

In this paper, characteristics of open transistor faults in cascaded H-bridge five-level three-phase PWM controlled shunt active power filter are determined. Phase currents can’t be trusted as fault indicator since their waveforms are slightly changed in the presence of open transistor fault. The proposed method uses H bridges output voltages to determine the faulty phase, the faulty bridge and more precisely, the open fault transistor.

The voltage-source inverters (VSI) supplying a motor drive are prone to open transistor faults. To address this issue in faulttolerant drives applicable to electric vehicles, a new open transistor fault diagnosis (FD) method is presented in this paper. According to the proposed method, in order to define the FD index, the phase angle of the converter output current is estimated by a simple trigonometric function. The proposed FD method is adaptable, simple, capable of detecting multiple open switch faults and robust to load operational variations. Keeping the FD in mind as a mandatory part of the fault tolerant control algorithm, the FD block is applied to a five-phase converter supplying a multiphase fault-tolerant PM motor drive with nonsinusoidal unbalanced current waveforms. To investigate the performance of the FD technique, the fault-tolerant sliding mode control (SMC) of a five-phase brushless direct current (BLDC) motor is developed in this paper with the embedded FD block. Once the theory is explained, experimental waveforms are obtained from a five-phase BLDC motor to show the effectiveness of the proposed FD method. The FD algorithm is implemented on a field programmable gate array (FPGA).