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We demonstrate a HfZrO2 (HZO) ferroelectric field-effect transistor fabricated on a silicon-on-insulator substrate, targeting MHz synaptic device applications. Stable multistate weights were implemented with robust retention, excellent linearity, and symmetric potentiation/depression (P/D) in the fabricated HZO ferroelectric field-effect transistors (FeFETs). To further improve the linearity and symmetry of the P/D and to expand the operating condition of the FeFETs as a synaptic device, a novel incremental drain-voltage-ramping method was proposed, and its compatibility was verified thoroughly. The results revealed that a linear and symmetric P/D with stable repeatability was obtained under a wide range of operating conditions, and a learning accuracy of 95% was achieved through MNIST pattern recognition simulations.

Synaptic devices, which are considered as one of the most important components of neuromorphic system, require a memory effect to store weight values, a high integrity for compact system, and a wide window to guarantee an accurate programming between each weight level. In this regard, memristive devices such as resistive random access memory (RRAM) and phase change memory (PCM) have been intensely studied; however, these devices have quite high current-level despite their state, which would be an issue if a deep and massive neural network is implemented with these devices since a large amount of current-sum needs to flow through a single electrode line. Organic transistor is one of the potential candidates as synaptic device owing to flexibility and a low current drivability for low power consumption during inference. In this paper, we investigate the performance and power consumption of neuromorphic system composed of organic synaptic transistors conducting a pattern recognition simulation with MNIST handwritten digit data set. It is analyzed according to threshold voltage (VT) window, device variation, and the number of available states. The classification accuracy is not affected by VT window if the device variation is not considered, but the current sum ratio between answer node and the rest 9 nodes varies. In contrast, the accuracy is significantly degraded as increasing the device variation; however, the classification rate is less affected when the number of device states is fewer.

In this study, we demonstrate both of digital and analog memory operations in InGaZnO (IGZO) memristor devices by controlling the electrode materials for neuromorphic application. The switching properties of the devices are determined by the initial energy barrier characteristics between the metal electrodes and the IGZO switching layer. Digital switching characteristics are obtained after the forming process when Schottky junction occurs at both of top and bottom electrodes. On the other hands, analog resistive switching is achieved when Schottky and Ohmic junctions exist at each side because the applied voltage modulates the Schottky barrier height through the Ohmic contact. In addition, the weight-update properties of the devices are verified depending on identical and incremental pulse schemes. The incremental pulse trains improve the linearity and variation of weight modulation, leading to the stable learning characteristics of neuromorphic system in terms of pattern recognition with MNIST hand-written digit images.

Multilevel operation is one of the most essential properties for synaptic devices to realize hardware artificial neural networks. Compliance current (Icc) adjustment is a multilevel programming method that can be utilized for a large-scale one-transistor and one-resistor (1T1R) array. It protects the devices from permanent breakdown by regulating abrupt switching. However, according to the reported literature so far, the number of conductance states in the Icc control method is insufficient to implement off-chip-trained neuromorphic systems. Therefore, we experimentally explore the feasibility of a larger number of conductance states using the Icc control method. We fabricated an Al2O3/TiOx-based resistive switching memory array, observed the conductance change while increasing Icc during set operations, and 64-level conductance states were statistically demonstrated. Furthermore, we verified that the 64-level states showed recognition performance close to that of a software-based neural network through off-chip learning of the convolutional neural network (CNN) structure. The fabricated synaptic device array with the Icc-control programming method is expected to contribute to the development of hardware neural network by reducing the information loss in the transfer process.