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This brief presents a detailed analysis on DAC-based current drivers implemented with bipolar technology. In many power applications, the need of speed and driving capability leads to the choice of bipolar transistors as driving elements, but such devices can suffer linearity issues in high accuracy applications. A method of discussion for such architectures is introduced, and the related analytical model provides a fast estimation of the linearity performances, favoring the choice of a convenient block floor-planning and an effective scrambling strategy. The theoretical computations are, then, compared with transistor level simulations results and, finally, validated by measurements, carried out on a circuit implementation manufactured in a 130-nm BiCMOS technology.

This article is devoted to a new circuit proposal for precision rectification, which is designed using current feedback operational amplifiers. The new proposed circuit operation is clearly discuss...

A low-voltage and low-power current mode rectifier based on dynamic threshold MOS (DTMOS) transistor is proposed in this paper. The suggested one input-two output rectifier architecture provides full-wave rectification and half-wave rectification. Full-wave rectifier consists of only 6 MOS transistors (excluding 1 MOS transistor in half-wave rectifier part) and is designed without the necessity of using active and passive circuit elements. The proposed rectifier design is simulated using 0.13 mu m IBM CMOS technology parameters. The full-wave rectifier circuit requires +/- 0.25 V of supply voltages and consumes only 4.36 nW thanks to employing DTMOS transistor structure.

This article presents a novel charge-controlled memristor emulator circuit. The proposed memristor emulator utilizes a single Current Follower Transconductance Amplifier (CFTA) as an active current mode analog building block and a grounded capacitor as a passive element. The circuit presented follows all the fingerprints of an ideal memristor. It operates in both incremental as well as decremental mode. The functional performance of the emulator circuit is verified at different operating frequencies and performs well up to 9 MHz. The theoretical and non-ideal analyses are verified for the proposed emulator. Moreover, Monte Carlo sampling and non-volatility analysis are performed to investigate the robustness of the emulator circuit. The functionality of the proposed model has been verified through PSPICE simulation using TSMC 0.18 $\mu m$ CMOS technology at the supply voltage of $\pm 1.2~V$ . The experimental confirmation of the presented circuit is also performed by building a breadboard micromodel using ICs CA3080 and AD844AN. Memristor based Chua’s circuit model is included as one of its applications.

The current–voltage characteristics measured on Ge2Sb2Te5 thin films in the current mode are studied. The effect of multilevel recording is established when applying sequential current pulses with increasing maxima. It is shown that this effect can be associated with memory-channel expansion. The memory-channel size is estimated. It is concluded that Ge2Sb2Te5 films can be used as memristors.

A low-voltage four-quadrant current-mode current-controllable zero/span circuit is discussed. The circuit structure is based on CMOS current follower with adjustable current gain and 4 diodes, without any resistor. The proposed circuit has advantage in such low-voltage architecture biased with as low as ±0.5V power supply. It can generate four-quadrant outputs, without any changing circuit topology. Additionally, its zero and span levels can be independently tuned by electronic method though relative bias currents, where a low-offset output current can be achieved. The total power consumption is approximately 10µW, much lower than a traditional one. Simulation results are shown; it offers good performances of the proposed circuit as depicted. Furthermore, to extend the workability of the proposed zero/span circuit, its application in current-mode Wheatstone bridge to alleviate the offset problem.

This paper introduces a novel structure for the realization of a low voltage, low power current-mode analog to the digital converter (ADC) pipeline (12 bits). The proposed structure of the ADC is based on a novel design of a current comparator and Digital to Analog Converter (DAC) structure. This modification allows us to reach a higher speed, lower voltage, and lower power dissipation. ELDO simulators using 0.18 μm, CMOS and TSMC parameters are performed to confirm the workability of this architecture. The proposed ADC is powered with a 1 V supply voltage. It is characterized by wide conversion frequency (350 MHz) and low power consumption that is 2.76 mW.

An extra-X second-generation current conveyor (EXCCII) based first-order current-mode all-pass frequency selective structure is presented through this paper. A grounded resistor and a grounded capacitor are used as passive components. Single active element based realization directly correlates with the circuit’s simplicity. The grounded nature of passive components is advantageous from IC fabrication aspects. The proposed circuit offers cascadability support through low input impedance and high output impedance. The ability of the presented idea to deliver the desired output without meeting any stringent component matching condition further simplifies the circuit’s operation. Sensitivity performance of the proposed circuit is good. The quality performance at high frequency is another value addition to the circuit’s signal processing attributes. Analyses showing the circuit’s behavior under non-ideal conditions are also described in detail. Validation of theoretical analyses is supported by simulations carried out on PSPICE at 0.25[Formula: see text][Formula: see text]m technology.

This brief presents a hybrid of voltage- and current-mode line drivers for the turbo controller area network (CAN). The current-mode scheme prevents signal attenuation caused by source termination resistors, and it enhances signal power efficiency. On top of that, an adaptive amplitude tuning is implemented to mitigate non-linearity and closed-loop gain variations against load impedance variations. The proposed line driver achieves 87.0% power-efficiency and total harmonic distortion, plus noise (THD+N) of −49.0 dB at an input frequency of 40 MHz and output swing of 2.8 VPP differential. The adaptive amplitude tuning allows load impedance variations from 80 Ω to 160 Ω. The total power consumption is 37.6 mW with a 1.8 V supply voltage in 180 nm CMOS, and it occupies 0.377 mm2.

The aim of this paper is to prove that, through a canonic approach, sinusoidal oscillators based on second-generation voltage conveyor (VCII) can be implemented. The investigation demonstrates the feasibility of the design results in a pair of new canonic oscillators based on negative type VCII (VCII−). Interestingly, the same analysis shows that no canonic oscillator configuration can be achieved using positive type VCII (VCII+), since a single VCII+ does not present the correct port conditions to implement such a device. From this analysis, it comes about that, for 5-node networks, the two presented oscillator configurations are the only possible ones and make use of two resistors, two capacitors and a single VCII−. Notably, the produced sinusoidal output signal is easily available through the low output impedance Z port of VCII, removing the need for additional voltage buffer for practical use, which is one of the main limitations of the current mode (CM) approach. The presented theory is substantiated by both LTSpice simulations and measurement results using the commercially available AD844 from Analog Devices, the latter being in a close agreement with the theory. Moreover, low values of THD are given for a wide frequency range.

In this paper, an area and power efficient current mode frequency synthesizer for system-on-chip (SoC) is proposed. A current-mode transformer loop filter suitable for low supply voltage is implemented to remove the need of a large capacitor in the loop filter, and a current controlled oscillator with additional voltage based frequency tuning mechanism is designed with an active inductor. The proposed design is further integrated with a fully programmable frequency divider to maintain a good balance among output frequency operating range, power consumption as well as silicon area. A test chip is implemented in a standard 0.13 µm CMOS technology, measurement result demonstrates that the proposed design has a working range from 916 MHz to 1.1 l GHz and occupies a silicon area of 0.25 mm2 while consuming 8.4 mW from a 1.2 V supply.

This paper proposes a multi-attractor period multi-scroll chaotic system and a second-generation current-controlled current conveyor (CCCII) with a wide tunable range of intrinsic resistance. The newly proposed multi-attractor period multi-scroll chaotic system is constructed by this CCCII. The proposed chaotic system can generate single-attractor period, double-attractor period, three-attractor period, and even more attractor period multi-scroll. The four-dimensional state equation of the chaotic system contains four nonlinear functions for generating multi-attractor period multi-scroll chaos. Since the intrinsic resistance of the CCCII can be adjusted by external voltages or currents, the multi-attractor period multi-scroll chaotic integrated circuit based on the proposed CCCII have a tunable characteristic. It is worth noting that a chaotic integrated circuit has been implemented completely using current signals instead of voltage signals, and more interestingly, it does not contain any passive resistor. The dynamic characteristics of the multi-attractor period multi-scroll chaotic system are given. The circuit designs of the CMOS CCCII and the corresponding chaotic circuit are made in detail. We conduct the numerical and circuit simulations of the proposed chaotic system and the integrated circuit implementation of the chaotic circuit based on the CMOS CCCII. The correctness of the CCCII circuit and the chaotic system are proved through hardware experiments. The comparison between the implementation scheme of the chaotic circuit in this paper and several reported chaotic circuits is conducted.

This contribution presents a design of a current-mode fractional-order electronically controllable integrator which can be used as a building block for a design of fractional-order (FO) circuits. The design is based on a 2nd-order Follow-the-Leader-Feedback topology which is suitably approximated to operate as an integrator of a fractional order. The topology is based on Operational Transconductance Amplifiers (OTAs), Adjustable Current Amplifiers (ACAs) and Current Follower (CF). The proposed structure offers the ability of the electronic control of its fractional order and also the electronic control of the frequency band. Simulations in Cadence IC6 (spectre) and more importantly experimental measurements were carried out to support the proposal. If wider bandwidth where the approximation is valid is required, a higher order structure must be used as also shown in this paper by utilization of a 4th_ order FLF topology.

In single-phase ac/dc applications where reliability and/or power-density are critical, active power decoupling (APD) circuits can be employed to reduce the required capacitance on the dc-link. Various APD circuits have been proposed so far, all with their advantages and disadvantages. However, many confusions still exist in the literature on this topic which is mainly attributed to a lack of unified and comprehensive assessment criteria. In this paper, first the decisive criteria for a modern APD circuit are established, and the buck APD is identified as the current state-of-the-art, based on them. Then the buck-plus-unfolder topology with triangular current mode (TCM) modulation is proposed as an improvement, and a simple, yet solid foundation is introduced to choose the superior decoupling solution at different specifications. The operation equations for the APD with TCM modulation are derived next, and the operation of the proposed solution is demonstrated using a hardware prototype.

This work presents the design of a discrete second-generation voltage conveyor (VCII) and its capability to be used as electronic interface for silicon photomultipliers. The design addressed here exploits directly at the transistor level, with commercial components, the proposed interface, the obtained performance is valuable considering both the discrete elements and the application. The architecture adopted here realizes a transimpedance amplifier that is also able to drive very high input impedance, as usually requested by photons detection. Schematic and circuital design of the discrete second-generation voltage conveyor is presented and discussed. The complete circuit interface requires a bias current of 20 mA with a dual 5V supply voltage, it has a useful bandwidth of about 106 MHz, and considering also the reduced dimensions, it is a good candidate to be used in portable applications without the need of high-cost dedicated integrated circuits.

In this paper we propose a new versatile full wave rectifier circuit using voltage conveyor (VCs) as active blocks. The proposed circuit uses two VCs, a single grounded resistor and two diodes. Compared to other previously reported rectifier circuits, it shows a simple and compact structure, employing the minimum possible number of elements. Moreover, the rectified output is available in forms of both voltage and current signals, at low impedance voltage output Z port and high impedance X port of VC, respectively. Therefore, for practical use, the proposed rectifier is cascadable without the need for extra voltage and current buffers. In addition, also the input signal can be applied in both forms of a current and of a voltage. To validate the presented theory, SPICE simulations, using 0.35 µm CMOS technology parameters and supply voltage of ±1.65 V, are reported, together with a set of measurements conducted over an equivalent discrete-level circuit, where AD844s were used to mimic VCs behavior.

In this paper, a new current-controlled memristor emulator circuit based on voltage differencing transconductance amplifier (VDTA) as an active circuit element is proposed. The proposed emulator circuit is simulated on the 180 nm CMOS technology node making it both cost and power-efficient emulator circuit. All the analytical derivations mentioned in this research work have been verified by simulation results obtained using virtuoso custom design platform of Cadence. The non-volatile nature of the proposed circuit has also been validated.

A new design for electronically tunable current mode (CM) instrumentation amplifier (IA) is presented in this paper. It employs Modified Z copy Current Differencing Transconductance Amplifier (MZC-CDTA) along with a resistor. The gain of the proposed CM IA is controlled by a single resistor and can theoretically approach infinite value. Electronic tuning feature is augmented by using a MOS based resistor. The functionality is verified through simulations on Cadence Virtuoso using TowerJazz’s 180 nm Technology Node and performance against PVT variations is also examined. Feasibility of on-chip implementation is confirmed by the post-layout simulations carried out.

Hybrid converter having ac and dc outputs, being single stage converter, is an interesting solution for dc nanogrid application. It offers independent control to both ac and dc output. The Buck-Boost-derived hybrid converter (BBDHC) proposed in this paper is capable of providing a wide range of buck/boost output voltage. For better understanding, a theoretical analysis of the converter in continuous current mode (CCM) and discontinuous current mode (DCM) is discussed. Unlike the conventional zero valued DCM, nonzero DCM (NZ-DCM) is a peculiar phenomenon observed in this converter. The NZ-DCM injects ripple in dc link voltage, deteriorating the performance and operation of BBDHC. To mitigate this, modified BBDHC (MBBDHC) is proposed. In MBBDHC, the NZ-DCM is replaced by forced CCM (FCCM). This modification permits the stable operation of MBBDHC under hybrid and standalone loads. Moreover, closed-loop study of MBBDHC is presented under load and voltage variations.

In this paper, a Current Mode Instrumentation Amplifier (CMIA) is presented. The proposed circuit employs two Extra X Current Controlled Current Conveyors (EX-CCCII) and a single grounded resistor. The circuit offers a wide differential-gain bandwidth, wide CMRR bandwidth, and electronically tunable differential gain. The circuit offers cascadibility feature with input impedance of 2.167 kΩ which is very small in comparison to the output impedance of 2.17 MΩ. Simultaneously, a Transresistance (TR) instrumentation amplifier is also obtained with the features of electronically tunable high differential gain and wide bandwidth. The effect of non-idealities of EX-CCCII on the circuit performance is also analysed. The validity of the proposed circuit is verified through PSPICE simulations using 0.25 µm parameters with a supply voltage of ±1.25 V. Also, the circuit is verified by experimental results.

Introduction. The mode of intermittent current for DC motor with three-phase thyristor rectifier appears in the idle intervals of some mechanisms. Active and passive filters reduce the variable component of the rectified voltage. The capacitance of the capacitors filter is determined by the effective value of the variable component of the rectified voltage. Problem. Necessity of developing an analytical method for calculating the effective value of the variable component of the rectified voltage in the intermittent current mode, taking into account three parameters: the control angle, the electromagnetic time constant of the armature circuit and the load current. Purpose. To determine the dependence of the effective value of the variable component of the rectified voltage for three parameters in theintermittent current mode. Methodology. The effective value of the variable component of the rectified voltage is suggested to be determined through the voltage pulsations factor as the ratio of the effective value of the variable component of the rectified voltage to its constant component. The dependence of the pulsations factor from the parameters of the mode is determined using computer simulation of the mode for intermittent current. Results . The computer model is developed in the software package Simulink, which allows to change each parameter of the mode separately while stabilizing the other two. Numerical dependences of the pulsation factor on each parameter are obtained. The analytical dependence of the voltage pulsations factor on three influencing values was obtained by the method of experiment planning. Originality. For the first time, method has been developed for calculating pulsation factor of the rectified voltage and calculating the effective value of the variable component in the mode of intermittent currents, taking into account three parameters. Practical value. The proposed method will allow to rationally determine the capacity of the capacitors of active and passive filters and increase the efficiency of electromechanical power conversion by reducing the variable component of the rectified voltage.

In this work, novel first order MOS-C phase shifter structures are proposed in NMOS and PMOS configurations. Core circuits consist of only three transistors and a single capacitor. The pole frequency of the phase shifters can be easily controlled by the bias voltage. The presented circuits in this work bring advantages such as low power consumption and small chip area when compared to other works including large numbers of active and passive elements in the literature. Furthermore, the proposed circuits are designed with a simple design automation flow that is proper for MOS-Only or MOS-C architectures. It is shown by simulations that the simulation results agree with the theoretical results for a wide frequency range. DOI: http://dx.doi.org/10.5755/j01.eie.24.1.20157

This article complements the cycle of previous works that were devoted to the evaluation of uncertainty of measurement results of cylindrical scintillators on the base of NaI(Tl), CsI(Tl), CWO, BGO, p-terphenyl, anthracene, stilbene and long length strips based on polystyrene (PS strip) technical light output in photons/MeV (ph/MeV). The comparison method with the working sample was used. The investigated scintillators were manufactured at the Institute for Scintillation Materials of the National Academy of Sciences of Ukraine (ISMA NASU). Technical light output of the scintillators was in the range from 38 ph/MeV for strips to 55000 ph/MeV for CsI(Tl).In this work, we compared the estimates of instrumental uncertainty of type B of the measurement results of the technical light output of scintillators using pulse and current measurement modes. Factors influencing the magnitude of instrumental measurement uncertainty are determined. The contributions of these factors to the instrumental uncertainty for specified measurement modes are evaluated. It is established that the value of instrumental measurement uncertainty is related to the limited sensitivity of the scale of analyzing instrument and depends on the number of divisions of the used scale and the location of the measured parameter on this scale. The calculated values of contributions’ estimates to the uncertainty of the measurement results of the technical light output of scintillators are in the range from 0.05 to 0.18 % for CsI(Tl) and from 0.95 to 2.45 % for strip No. 1.Based on the results of the instrumental uncertainty estimates received in this work and taking into account the results of previous studies, the measurement uncertainty budgets for the technical light output of scintillators based on CsI(Tl) (pulse mode) and strip No. 3 (current mode) are compiled.

This paper presents a 16‐channel power‐efficient neural/muscular stimulation integrated circuit for peripheral nerve prosthesis. First, the theoretical analysis is presented to show the power efficiency optimization in a stimulator. Moreover, a continuous‐time, biphasic exponential‐current‐waveform generation circuit is designed based on Taylor series approximation and implemented in the proposed stimulation chip to optimize the power efficiency. Finally, the chip is implemented and the maximum stimulation power efficiency of 95.9% is achieved at the output stage of the stimulator in the measurement.

A novel current-mode (CM) universal filter configuration composed of five plus-type second-generation current conveyors (CCII+s) as active components besides three resistors and three grounded capacitors as passive elements is proposed in this paper. The proposed filter can simultaneously provide high-pass, band-pass and low-pass responses. Also, it can realize all-pass and notch responses with interconnection of convenient output currents. It can be cascaded with other CM ones easily because it has low input and high output impedances. It offers orthogonal control of angular resonance frequency and quality factor. An electronically tunable universal filter can be easily obtained if plus-type current controlled current conveyors are replaced instead of each of the five CCII+s and all the three resistors are removed. Nevertheless, it needs a single passive element matching constraint for notch and all-pass filter responses. Some simulation and experimental test results are included to confirm the theory. © 2017 Elsevier GmbH

This paper, proposes a low-voltage/power, high-speed configurable analog block (CAB) for current-mode nonlinear computation. A novel MOS translinear cell (MTC), two local switch networks and PMOS-NMOS arrays are the basic building blocks of the proposed CAB. This MTC consists of two overlapped translinear loops using the MOS transistors operating in weak inversion region. The proposed CAB is capable to implement such current-mode analog computational processors as one- and four-quadrant multipliers, one- and two-quadrant dividers, squarer, full-wave rectifier (absolute-value), RMS to DC converter and much other. Post-layout plus Monte Carlo simulations of the proposed design with 0.18 µm (level-49 parameters) TSMC technology is performed that prove its superiority over some other advanced works and robustness against process, voltage and temperature variations. This superb feature plus many others, mostly, are due to the precise multilateral analysis and optimal compensate of mismatches and second order effects of the proposed circuit that led to proper selection of devices sizes and deliberate arrangement of the layout.

The article describes main methods for regulation of the secondary voltage of furnace transformers (FT) of high-power arc steel furnaces (ASF), their advantages and drawbacks are outlined. Within consideration of the non-contact and high-speed regulation of FT voltage, the emphasis is put on using thyristor voltage regulator deployed in the intermediate circuit. The comparative evaluation of main energy indicators of the FT-ASF complex are given within using thyristor regulator of secondary FT voltage, and of traditional methods for controlling electric modes of ASFs by means of affecting the furnace transformed as the high-speed executive component of the regulation system. Main electric modes that can be obtained through using thyristor regulator of the furnace transformer in case of supporting the constant primary current in the FT, are considered. Results are obtained using a math model of the FT-ASF electrotechnical complex, developed in MATLAB Simulink package.

Current-mode signalling scheme is one of the prominent solutions for high-speed and high data rate communication in global on-chip interconnects. Advancements in nanofabrication processes and housi...

International audience; Power estimation of a DBD device supplied by a current source converter is studied in this article, pointing out the prominent contribution of the transformer parasitic elements. The impact of the stray capacitance and magnetizing inductance is stated and an iterative method that estimates the electrical power and DBD waveforms is presented. Results show that the magnetizing inductance can enhance the electrical power without changing the current ratings of the converter and that the stray capacitance must be minimized. Moreover, the experimental results reveal the need for a better DBD model to properly estimate the power. In consequence, an improved model is proposed and validated using a DBD excimer lamp in a wide range of electrical operating conditions.

This paper presents the design of a system aimed at characterizing a diverse set of dielectric barrier discharge UV lamps. This experimental bench allows the study of the lamps performances regarding UV emission maximization and energy conversion optimization. It includes a current-mode pulsed power supply for the lamps, the design of which is detailed. This converter presents 3 degrees of freedom (DOF) can control and adjust independently the frequency, amplitude and duration of the current pulses injected into the lamps. Theoretical modeling of the lamps, by means of equivalent electrical circuits, is used to define the most interesting operating points to be explored, as well as for the converter’s design; these models are afterwards validated by experimental tests on the entire set of lamps. The operation of the bench is controlled by a supervising program: the latter manages the data acquisition and performs sweeps of the DOFs of the pulsed current. Examples of analyzes, oriented toward optimization of electric to UV energy conversion, are shown.

Electronic load (e-load) is essential equipment for power converter performance test, where a designated load profile is executed. Electronic load is usually implemented with the analog controller for fast tracking of the load profile reference. In this paper, a low-power low-cost electronic load is proposed. MOSFETs (metal-oxide-semiconductor field-effect transistors) are used as the power consumption devices, which are regulated to the active region as controlled current-sink. In order to achieve fast transient response using the low-cost digital signal controller (DSC) PWM peripherals, the interleaving PWM method is proposed to achieve active current ripple mitigation. To obtain the system open-loop gain for current-sink operation, an offline digital system identification method, followed by model reduction, is proposed by applying Pseudo-Random Binary Sequence (PRBS) excitation. Pole-zero cancelation method is used in the control system design and later implemented in a DSC. The prototype is built and tested, in which meaningful testing scenarios under constant current-sink mode, pulse current sink mode, and double line-frequency current mode are verified. The experimental results indicate that the proposed e-load can sink pre-programmed current profile with well-attenuated ripple for static and dynamic load testing, and is applicable to fully digitalized power testing equipment.

This paper proposes to apply discontinuous current mode (DCM) for motor drive inverters to avoid the problems caused by high dv/dt in output, with relatively small filter components. A three-phase configuration for the DCM operation is proposed and a direct current control method and its application to PMSG drive are discussed. The experimental demonstration with a 2-kW PMSM are shown.

In this paper, a new low-voltage low-power dual-mode universal filter is presented. The proposed circuit is implemented using inverting current buffer (I-CB) and second-generation voltage conveyors (VCIIs) as active building blocks and five resistors and three capacitors as passive elements. The circuit is in single-input multiple-output (SIMO) structure and can produce second-order high-pass (HP), band-pass (BP), low-pass (LP), all-pass (AP), and band-stop (BS) transfer functions. The outputs are available as voltage signals at low impedance Z ports of the VCII. The HP, BP, AP, and BS outputs are also produced in the form of current signals at high impedance X ports of the VCIIs. In addition, the AP and BS outputs are also available in inverting type. The proposed circuit enjoys a dual-mode operation and, based on the application, the input signal can be either current or voltage. It is worth mentioning that the proposed filter does not require any component matching constraint and all sensitivities are low, moreover it can be easily cascadable. The simulation results using 0.18 &mu, m CMOS technology parameters at a supply voltage of &plusmn, 0.9 V are provided to support the presented theory.

This paper presents a current mode quadrature oscillator using current differencing transconductance amplifier (CDTA). The proposed circuit uses a single CDTA, one resistor, and two capacitors. The designed circuit enjoys the advantages of independent control of condition of oscillation (CO) and frequency of oscillation (FO). The performance of the proposed circuit is examined using PSPICE with model parameters of TSMC 0.18 µm.

In the paper, the theory of pseudo-differential filters is examined and supported by designing a fourth-order frequency filter operating in current mode and implemented as cascade connection of two basic second-order blocks. The basic block employs three current conveyors as active elements and four passive elements. The filter is characterized by a high output impedance, and minimum number of passive elements, whereas capacitors are grounded. To prove the operability of the final filter, the partial second-order pseudo-differential filters were interconnected in four different ways. The simulation results of the each interconnection prove proper behavior of pseudo-differential filters in analogue signal processing.

This paper presents an electronically tunable multiphase sinusoidal oscillator, employing three grounded capacitors and two EX-CCCIIs. The proposed circuit provides the current output as well as voltage outputs. The multiphase output currents obtained at high impedances so there is no need of any sensing circuit to sense the current. Also, the proposed circuit parameters: oscillation frequency (ω o ) and condition of oscillation (C.O.) are independent, as well as the ω o , can be tuned with bias currents. The design verification of the proposed circuit is included with the attractive results through the PSPICE program.

Introduction: Recurrent ventricular arrhythmias (VA) are a source of significant morbidity in patients without structural heart disease (SHD) and also mortality in patients with SHD. The treatment goals for these two patient populations differ greatly.Areas covered: The secondary prevention of recurrent VA in patients without and with SHD will be reviewed, focusing on clinical data (especially randomized, controlled trials) in the literature as determined through searches in PubMed and ClinicalTrials.gov. This will include β blockers, non-dihydropyridine calcium channel blockers and antiarrhythmic drugs in both subgroups and non-antiarrhythmic medications in SHD.Expert commentary: The available options for medical therapy for VA in both normal hearts and SHD are insufficient, due to substandard efficacy and toxicities. While non-pharmacologic therapies may provide an excellent option, further drug development and randomized trials are needed, as is a reappraisal of the current mode of utilization.

The performance of current-mode signaling (CMS) scheme in carbon nanomaterial based multiwall carbon nanotube (MWCNT) bundle on-chip interconnect using finite-difference time-domain (FDTD) technique is investigated in the present paper. A very comprehensive model that analyzes both the traditional copper and the next-generation MWCNT bundle interconnects is presented. Further, this model is applicable for both the conventional voltage-mode signaling (VMS) and the delay-efficient CMS schemes. The number of MWCNT shells in a bundle interconnect is varied, and it is analyzed that MWCNTs with larger number of shells have better performance than both MWCNTs consisting of lesser number of shells and the copper interconnects. It is analyzed that CMS scheme has superior performance than VMS scheme in terms of smaller propagation delay and reduced crosstalk-induced delay. Various analyses have been performed for 32-nm technology node and are validated using SPICE simulations. The results obtained from the proposed FDTD based model and SPICE are found to be in close agreement, and the maximum error is within 3%.

The paper presents a second order current mode sigma-delta modulator designed with the help of a new elaborated tool to optimize the transistor sizes. The circuit is composed of two continuous time loop filters, a current comparator and a one bit DAC with a current output. The resulting circuit, designed in a 65 nm 1.2 V CMOS technology, has a bandwidth of 2 MHz for a clock frequency of 250 MHz. The electrical simulation results show that it achieves a maximum signal-to-noise-plus-distortion ratio (SNDR) of 53.6 dB while dissipating 93 μW, which corresponds to an efficiency of 59.7 fJ/conv. The fully current mode structure makes the circuit suitable to be applied in a current mode signal processing like biosensors or image pixels arrays.

A new type of quaternary D flip-flop based on multiple-valued current-mode is presented for high-speed sequential circuit in VLSI systems. It employs master-slave mode and dynamic multiple-valued source-coupled logic. A distinguishable multiple-valued interval, fast switch speed and compact structure are obtained by combining source-coupled logic with differential-pair circuit. The performance evaluation is carried out with HSPICE using 0.18μm CMOS process. A performance comparison with those issued in some references is conducted. The delay in our design is about 74% reduced by comparison with the corresponding binary implementation. The circuitry proposed is simplicity, regularity, and modularity, so well suited for VLSI implementation. Quaternary logic seems to be a potential and feasible method of high-performance VLSI systems.

The effect of electric current assisted annealing was investigated in amorphous Fe40Ni40B20 melt spun ribbons in terms of manipulating the crystallization temperature and phase formation. A specific setup was developed, which allows to measure the sample temperature and the electrical resistance in-situ during the annealing process. By employing these simultaneous measurements, the shift of the crystallization temperature was evaluated by employing different electric current modes and current densities. It was found that the onset temperature for crystallization is shifted to lower temperatures when a certain threshold of electric current density is surpassed. Maximum temperature shifts up to 130°C were achieved using direct and alternate current modes, while in pulsed current mode the maximum shift was 100°C. Even though a noticeable change was observed in the crystallization temperature when an electric current is applied during annealing, the nucleated phases were found to be the same as in the samples annealed without current. The reasons for the observed behavior are discussed and compared to propositions found in the literature. It is concluded that the ‘‘hot spots’’ mechanism is in good agreement with the results obtained in this work.

A novel three-level zero-current-switching (ZCS) converter, operating in discontinuous current mode, is proposed for the application of distributed photovoltaic power accessing the medium voltage dc distribution network. The proposed converter is composed of a traditional neutral point clamped (NPC) three-level (TL) circuit and an auxiliary circuit, owning 6 switches and 2 transformers. By controlling the auxiliary circuit with Pulse width modulation (PWM), ZCS can be reached for the basic TL circuit, which delivers most of the power, with the switching loss of the converter remarkably reduced. The influence of turn’s ratio the auxiliary transformer on the switch current is discussed in detail, and the parameters design principles are put forward, which is verified with PLECS simulation results. Finally, a prototype of 300 V-1500 V/1500W is built to verify the performance of the proposed converter.

Current chapter deals with Wheatstone Bridges with the focus on Current-Mode Wheatstone Bridge and its associated signal conditioning circuits. The operation, advantages and drawbacks of each circuit are discussed in detail. To make the comparison between traditional Voltage-Mode Wheatstone Bridge and Current-Mode Wheatstone Bridge more convenient, at the beginning of this chapter, the concept of Voltage-Mode Wheatstone Bridge is briefly summarized. The theory of Mixed-Mode Wheatstone Bridge and read-out circuits are also included. © 2019, Springer Nature Switzerland AG.

A physically unclonable function (PUF) using organic thin film transistors (oTFT) is proposed. The proposed current-mode arbiter PUF (CMA-PUF) operates in current-mode wherein sums of the transistor currents are compared to generate a response while the conventional arbiter PUF generates its response according to the sums of the delay of the logic gates. Owing to the simple construct of the CMA-PUF, the number of transistors has been reduced, enabling a compact and robust layout using oTFTs. We compare performance metrics and layouts between the proposed and existing arbiter PUFs. The results show that the proposed CMA-PUF utilizing oTFT achieves similar performance while the occupied area of circuit is reduced by approximately 52% than the existing arbiter PUF.

Currently known designs of Time-Based ADCs using successive sub-ranging technique have inherent drawback due to finite discharging-time of second capacitor when the first is already charged and fed to one end of comparator. This adds an undesired error in conversion and adversely affects the accuracy, ENOB and SNDR. This paper proposes an improvement to the design through a novel technique by adding a third capacitor, which allows the second capacitor to discharge without introducing any error. To accommodate this, a modified algorithm has been developed and a new state machine has been designed and presented. The modified design still preserves the merits of error-cancellation and energy efficiency. Design and simulation results using Cadence Virtuoso, 45nm GPDK technology is presented.

This paper presents how the parasitic elements of the step-up transformer impact the DBD operation, while supplied with a current-mode converter. The initial analysis is performed with the state-plane technique and then the steady-state values are calculated with an iterative method. Results show that the increase of power in the DBD can be achieved by the reduction of the magnetizing inductance and the parasitic capacitance in the transformer, without changing the power converter ratings. This result offers the opportunity to achieve a revision of the transformer specifications; and it is advantageous in terms of dimensions and price of the latter. Experimental results are performed with UV excilamps verifying the analysis. The need of a more complex DBD model has been also pointed out, to extend the validity of the presented method in the case of short current pulses.

Bio-sensors are important parts of systems monitoring biological processes. Some of the techniques, applied in this type of sensors convert a physical/chemical phenomenon into an electrical current. Important part of such measurement devices is a ADC. The paper reported several structures of current mode Sigma-Delta modulators with ultra-low power consumption and other parameters suitable for this class of systems. An integrator based on a current mirror structure is used as a noise shaping filter. The presented design approach uses the VHDL-AMS models. A final, transistor level structure is also reported.

DC networks have generated much interest in recent years, from transmission in high voltage to their use in distribution systems. One of the major challenges is to replace the high efficient and reliable ac transformer, especially at high voltage and step ratio. New resonant modular multilevel topologies have arisen as an alternative, mainly because of advantages such as optional use of transformers, natural voltage balance, simple control and soft-switching. However, this type of operation generates a high peak current, does not allow control of power flow in all power range and has a limited range of voltage variation. This paper proposes an asymmetrical triangular current mode applied in high step ratio Modular Multilevel dc-dc Converters that achieves bidirectional control of the power, soft-switching and a natural balance of the voltage in the capacitors. The simulation results show the bidirectional operation and the capacitor voltage balance of the converter under different operating conditions with high efficiency and low peak current compared to resonant mode. The proposal was tested in a down-scale prototype, confirming the operation principle.